• Jinyang He's avatar
    MIPS: KASLR: Avoid endless loop in sync_icache if synci_step is zero · c0aac3a5
    Jinyang He authored
    Most platforms do not need to do synci instruction operations when
    synci_step is 0. But for example, the synci implementation on Loongson64
    platform has some changes. On the one hand, it ensures that the memory
    access instructions have been completed. On the other hand, it guarantees
    that all prefetch instructions need to be fetched again. And its address
    information is useless. Thus, only one synci operation is required when
    synci_step is 0 on Loongson64 platform. I guess that some other platforms
    have similar implementations on synci, so add judgment conditions in
    `while` to ensure that at least all platforms perform synci operations
    once. For those platforms that do not need synci, they just do one more
    operation similar to nop.
    Signed-off-by: default avatarJinyang He <hejinyang@loongson.cn>
    Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
    c0aac3a5
relocate.c 10.7 KB