This adds a new driver for the USB3 PHY found on Meson GXL and GXM SoCs
(both SoCs are using the same USB PHY register layout).

Unfortunately there is no documentation for this PHY in the public S905X
datasheet (published for example by Khadas). What we know so far about
this PHY:
- even though the Meson GXL and GXM SoCs do not expose an USB3 port (the
  dwc3 controller only has USB2 ports enabled) we need to initialize the
  USB3 PHY (specifically USB_R1_U3H_FLADJ_30MHZ_REG_MASK). Without this
  initialization high-speed USB devices (especially USB hard disks and
  thumb drives, slower devices like mice do not seem to be affected)
- on some boards the USB3 PHY starts in "device mode" - we want to bring
  it into a known state (by switching it to host mode for now).
- it is responsible for the OTG detection and for switching the first
  USB2 PHY between host and peripheral (aka device) mode. an interrupt
  can be used to detect changes between host and device mode.

There are five inputs to this register area:
- the clock and reset line for the USB3 PHY itself
- the clock and reset line for the peripheral mode and OTG detection
  logic (on the GXL and GXM SoCs these are the same clock and reset line
  as for the USB3 PHY itself, but Amlogic sees this as two different
  components - even though they share the same register space - so they
  have to be passed individually to allow specifying different inputs on
  other SoCs if needed)
- the interrupt for the OTG detection logic

The whole OTG detection logic is not implemented yet.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Yixun Lan <yixun.lan@amlogic.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>