• Andi Kleen's avatar
    x86/speculation/l1tf: Increase l1tf memory limit for Nehalem+ · cc51e542
    Andi Kleen authored
    On Nehalem and newer core CPUs the CPU cache internally uses 44 bits
    physical address space. The L1TF workaround is limited by this internal
    cache address width, and needs to have one bit free there for the
    mitigation to work.
    
    Older client systems report only 36bit physical address space so the range
    check decides that L1TF is not mitigated for a 36bit phys/32GB system with
    some memory holes.
    
    But since these actually have the larger internal cache width this warning
    is bogus because it would only really be needed if the system had more than
    43bits of memory.
    
    Add a new internal x86_cache_bits field. Normally it is the same as the
    physical bits field reported by CPUID, but for Nehalem and newerforce it to
    be at least 44bits.
    
    Change the L1TF memory size warning to use the new cache_bits field to
    avoid bogus warnings and remove the bogus comment about memory size.
    
    Fixes: 17dbca11 ("x86/speculation/l1tf: Add sysfs reporting for l1tf")
    Reported-by: default avatarGeorge Anchev <studio@anchev.net>
    Reported-by: default avatarChristopher Snowhill <kode54@gmail.com>
    Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
    Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
    Cc: x86@kernel.org
    Cc: linux-kernel@vger.kernel.org
    Cc: Michael Hocko <mhocko@suse.com>
    Cc: vbabka@suse.cz
    Cc: stable@vger.kernel.org
    Link: https://lkml.kernel.org/r/20180824170351.34874-1-andi@firstfloor.org
    cc51e542
processor.h 25 KB