• Anup Patel's avatar
    RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls · 92ad8200
    Anup Patel authored
    For KVM RISC-V, we use KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls to access
    VCPU config and registers from user-space.
    
    We have three types of VCPU registers:
    1. CONFIG - these are VCPU config and capabilities
    2. CORE   - these are VCPU general purpose registers
    3. CSR    - these are VCPU control and status registers
    
    The CONFIG register available to user-space is ISA. The ISA register is
    a read and write register where user-space can only write the desired
    VCPU ISA capabilities before running the VCPU.
    
    The CORE registers available to user-space are PC, RA, SP, GP, TP, A0-A7,
    T0-T6, S0-S11 and MODE. Most of these are RISC-V general registers except
    PC and MODE. The PC register represents program counter whereas the MODE
    register represent VCPU privilege mode (i.e. S/U-mode).
    
    The CSRs available to user-space are SSTATUS, SIE, STVEC, SSCRATCH, SEPC,
    SCAUSE, STVAL, SIP, and SATP. All of these are read/write registers.
    
    In future, more VCPU register types will be added (such as FP) for the
    KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
    Signed-off-by: default avatarAnup Patel <anup.patel@wdc.com>
    Acked-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
    Reviewed-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
    Acked-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
    92ad8200
kvm.h 2.39 KB