Some SoCs support only pin change interrupts on GPIO pins used as irq
lines.

The ads7846 core is not affected from the additional irqs on the rising
edge because the code accounts touch bounce anyway by kicking in a timer
and disabling the irq after the first request and reenabling the irq after
a timeout when there is no longer pen down detected.
Signed-off-by: Michael Roth <mroth@nessie.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Dmitry Torokhov <dtor@mail.ru>