• Ahmad Fatoum's avatar
    clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz · 72d00e56
    Ahmad Fatoum authored
    Since commit b09c68dc ("clk: imx: pll14xx: Support dynamic rates"),
    the driver has the ability to dynamically compute PLL parameters to
    approximate the requested rates. This is not always used, because the
    logic is as follows:
    
      - Check if the target rate is hardcoded in the frequency table
      - Check if varying only kdiv is possible, so switch over is glitch free
      - Compute rate dynamically by iterating over pdiv range
    
    If we skip the frequency table for the 1443x PLL, we find that the
    computed values differ to the hardcoded ones. This can be valid if the
    hardcoded values guarantee for example an earlier lock-in or if the
    divisors are chosen, so that other important rates are more likely to
    be reached glitch-free.
    
    For rates (393216000 and 361267200, this doesn't seem to be the case:
    They are only approximated by existing parameters (393215995 and
    361267196 Hz, respectively) and they aren't reachable glitch-free from
    other hardcoded frequencies. Dropping them from the table allows us
    to lock-in to these frequencies exactly.
    
    This is immediately noticeable because they are the assigned-clock-rates
    for IMX8MN_AUDIO_PLL1 and IMX8MN_AUDIO_PLL2, respectively and a look
    into clk_summary so far showed that they were a few Hz short of the target:
    
    imx8mn-board:~# grep audio_pll[12]_out /sys/kernel/debug/clk/clk_summary
    audio_pll2_out           0        0        0   361267196 0     0  50000   N
    audio_pll1_out           1        1        0   393215995 0     0  50000   Y
    
    and afterwards:
    
    imx8mn-board:~# grep audio_pll[12]_out /sys/kernel/debug/clk/clk_summary
    audio_pll2_out           0        0        0   361267200 0     0  50000   N
    audio_pll1_out           1        1        0   393216000 0     0  50000   Y
    
    This change is equivalent to adding following hardcoded values:
    
      /*               rate     mdiv  pdiv  sdiv   kdiv */
      PLL_1443X_RATE(393216000, 655,    5,    3,  23593),
      PLL_1443X_RATE(361267200, 497,   33,    0, -16882),
    
    Fixes: 053a4ffe ("clk: imx: imx8mm: fix audio pll setting")
    Cc: stable@vger.kernel.org # v5.18+
    Signed-off-by: default avatarAhmad Fatoum <a.fatoum@pengutronix.de>
    Signed-off-by: default avatarMarco Felsch <m.felsch@pengutronix.de>
    Link: https://lore.kernel.org/r/20230807084744.1184791-2-m.felsch@pengutronix.deSigned-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
    72d00e56
clk-pll14xx.c 13.5 KB