• Stephen Boyd's avatar
    ARM: msm: Rework timer binding to be more general · eebdb0c1
    Stephen Boyd authored
    The msm timer binding I wrote is bad. First off, the clock
    frequency in the binding for the dgt is wrong. Software divides
    down the input rate by 4 to achieve the rate listed in the
    binding. We also treat each individual timer as a separate
    hardware component, when in reality there is one timer block
    (that may be duplicated per cpu) with multiple timers within it.
    Depending on the version of the hardware there can be one or two
    general purpose timers, status and divider control registers, and
    an entirely different register layout.
    
    In the next patch we'll need to know about the different register
    layouts so that we can properly check the status register after
    clearing the count. The current binding makes this complicated
    because the general purpose timer's reg property doesn't indicate
    where that status register is, and in fact it is beyond the size
    of the reg property.
    
    Clean all this up by just having one node for the timer hardware,
    and describe all the interrupts and clock frequencies supported
    while having one reg property that covers the entire timer
    register region. We'll use the compatible field in the future to
    determine different register layouts and if we should read the
    status registers, etc.
    Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
    Signed-off-by: default avatarDavid Brown <davidb@codeaurora.org>
    eebdb0c1
timer.txt 1.2 KB