• Atish Patra's avatar
    RISC-V: Avoid using per cpu array for ordered booting · 9a2451f1
    Atish Patra authored
    Currently both order booting and spinwait approach uses a per cpu
    array to update stack & task pointer. This approach will not work for the
    following cases.
    1. If NR_CPUs are configured to be less than highest hart id.
    2. A platform has sparse hartid.
    
    This issue can be fixed for ordered booting as the booting cpu brings up
    one cpu at a time using SBI HSM extension which has opaque parameter
    that is unused until now.
    
    Introduce a common secondary boot data structure that can store the stack
    and task pointer. Secondary harts will use this data while booting up
    to setup the sp & tp.
    Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
    Signed-off-by: default avatarAtish Patra <atishp@rivosinc.com>
    Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
    9a2451f1
asm-offsets.c 19.5 KB