• Daniel Vetter's avatar
    drm/i915: Fix up PSR frontbuffer tracking · 9ca15301
    Daniel Vetter authored
    I've tried to split this up, but all the changes are so tightly
    related that I didn't find a good way to do this without breaking
    bisecting. Essentially this completely changes how psr is glued into
    the overall driver, and there's not much you can do to soften such a
    paradigm change.
    
    - Use frontbuffer tracking bits stuff to separate disable and
      re-enable.
    
    - Don't re-check everything in the psr work. We have now accurate
      tracking for everything, so no need to check for sprites or tiling
      really. Allows us to ditch tons of locks.
    
    - That in turn allows us to properly cancel the work in the disable
      function - no more deadlocks.
    
    - Add a check for HSW sprites and force a flush. Apparently the
      hardware doesn't forward the flushing when updating the sprite base
      address. We can do the same trick everywhere else we have such
      issues, e.g. on baytrail with ... everything.
    
    - Don't re-enable psr with a delay in psr_exit. It really must be
      turned off forever if we detect a gtt write. At least with the
      current frontbuffer render tracking. Userspace can do a busy ioctl
      call or no-op pageflip to re-enable psr.
    
    - Drop redundant checks for crtc and crtc->active - now that they're
      only called from enable this is guaranteed.
    
    - Fix up the hsw port check. eDP can also happen on port D, but the
      issue is exactly that it doesn't work there. So an || check is
      wrong.
    
    - We still schedule the psr work with a delay. The frontbuffer
      flushing interface mandates that we upload the next full frame, so
      need to wait a bit. Once we have single-shot frame uploads we can do
      better here.
    
    v2: Don't enable psr initially, rely upon the fb flush of the initial
    plane setup for that. Gives us more unified code flow and makes the
    crtc enable sequence less a special case.
    
    v3: s/psr_exit/psr_invalidate/ for consistency
    
    v4: Fixup whitespace.
    
    v5: Correctly bail out of psr_invalidate/flush when
    dev_priv->psr.enabled is NULL. Spotted by Rodrigo.
    
    v6:
    - Only schedule work when there's work to do. Fixes WARNINGs reported
      by Rodrigo.
    - Comments Chris requested to clarify the code.
    
    v7: Fix conflict on rebase (Rodrigo)
    
    Cc: Chris Wilson <chris@chris-wilson.co.uk>
    Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
    Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v6)
    Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    9ca15301
intel_dp.c 129 KB