• Bruce Allan's avatar
    e1000e: 82579 potential system hang on stress when ME enabled · bdc125f7
    Bruce Allan authored
    Previously, a workaround was added to address a hardware bug in the
    PCIm2PCI arbiter where a write by the driver of the Transmit/Receive
    Descriptor Tail register could happen concurrently with a write of any
    MAC CSR register by the Manageability Engine (ME) which could cause the
    Tail register to have an incorrect value.  The arbiter is supposed to
    prevent the concurrent writes but there is a bug that can cause the Host
    (driver) access to be acknowledged later than it should.
    After further investigation, it was discovered that a driver write access
    of any MAC CSR register after being idle for some time can be lost when
    ME is accessing a MAC CSR register.  When this happens, no further target
    access is claimed by the MAC which could hang the system.
    The workaround to check bit 24 in the FWSM register (set only when ME is
    accessing a MAC CSR register) and delay for a limited amount of time until
    it is cleared is now done for all driver writes of MAC CSR registers on
    82579 with ME enabled.  In the rare case when the driver is writing the
    Tail register and ME is accessing any MAC CSR register for a duration
    longer than the maximum delay, write the register and verify it has the
    correct value before continuing, otherwise reset the device.
    
    This patch also moves some pre-existing macros from the hardware-specific
    header file to the more appropriate generic driver header file.
    Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
    Tested-by: default avatarJeff Pieper <jeffrey.e.pieper@intel.com>
    Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
    bdc125f7
e1000.h 27.6 KB