• Greg Ungerer's avatar
    m68k: generalize io memory region setup for ColdFire ACR registers · 8cf4a973
    Greg Ungerer authored
    The ACR registers of the ColdFire define at a macro level what regions
    of the addresses space should have caching or other attribute types applied.
    
    Currently for the MMU enabled setups we map the interal IO peripheral addres
    space as uncachable based on the define for the MBAR address (CONFIG_MBAR).
    Not all ColdFire SoC use a programmable MBAR register address. Some parts
    have fixed addressing for their internal peripheral registers.
    
    Generalize the way we get the internal peripheral base address so all types
    can be accomodated in the ACR definitions. Each ColdFire SoC type now sets
    its IO memory base and size definitions (which may be based on MBAR) which
    are then used in the ACR definitions.
    Signed-off-by: default avatarGreg Ungerer <gerg@linux-m68k.org>
    8cf4a973
m54xxsim.h 3.49 KB