• Vladimir Oltean's avatar
    net: dsa: sja1105: Add support for the SGMII port · ffe10e67
    Vladimir Oltean authored
    SJA1105 switches R and S have one SerDes port with an 802.3z
    quasi-compatible PCS, hardwired on port 4. The other ports are still
    MII/RMII/RGMII. The PCS performs rate adaptation to lower link speeds;
    the MAC on this port is hardwired at gigabit. Only full duplex is
    supported.
    
    The SGMII port can be configured as part of the static config tables, as
    well as through a dedicated SPI address region for its pseudo-clause-22
    registers. However it looks like the static configuration is not
    able to change some out-of-reset values (like the value of MII_BMCR), so
    at the end of the day, having code for it is utterly pointless. We are
    just going to use the pseudo-C22 interface.
    
    Because the PCS gets reset when the switch resets, we have to add even
    more restoration logic to sja1105_static_config_reload, otherwise the
    SGMII port breaks after operations such as enabling PTP timestamping
    which require a switch reset.
    
    >From PHYLINK perspective, the switch supports *only* SGMII (it doesn't
    support 1000Base-X). It also doesn't expose access to the raw config
    word for in-band AN in registers MII_ADV/MII_LPA.
    It is able to work in the following modes:
     - Forced speed
     - SGMII in-band AN slave (speed received from PHY)
     - SGMII in-band AN master (acting as a PHY)
    
    The latter mode is not supported by this patch. It is even unclear to me
    how that would be described. There is some code for it left in the
    patch, but 'an_master' is always passed as false.
    Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
    Reviewed-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    ffe10e67
sja1105_sgmii.h 1.75 KB