• Imre Deak's avatar
    drm/i915/dp_mst: Reduce the link parameters in BW order after LT failures · aa705f7e
    Imre Deak authored
    On MST links - at least for some MST branch devices - the list of modes
    returned to users on an enabled link depends on the current link
    rate/lane count parameters (besides the DPRX link capabilities, any MST
    branch BW limit and the maximum link parameters reduced after LT
    failures). In particular the MST branch BW limit may depend on the link
    rate/lane count parameters programmed to DPCD. After an LT failure and
    limiting the maximum link parameters accordingly, users should see a
    mode list reflecting these new limits. However with the current fallback
    order this isn't ensured, as the new limit could allow for modes
    requiring a higher link BW, but these modes will be filtered out due to
    the enabled link's lower link BW.
    
    Ensure that the mode list changes in a consistent way after a link
    training failure and reducing the link parameters by changing the
    fallback order on MST links to happen in BW order.
    
    v2:
    - s/INTEL_DP_MAX_SUPPORTED_LANE_COUNTS/INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS
      and s/num_common_lane_counts/num_common_lane_configs to make the
      difference wrt. max lane counts clearer. (Suraj)
    - Add a TODO comment to make the SST fallback logic work the same way as
      MST. (Arun)
    - Use sort_r()'s default swap function instead of a custom one.
    
    Cc: Suraj Kandpal <suraj.kandpal@intel.com>
    Cc: Arun R Murthy <arun.r.murthy@intel.com>
    Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
    Reviewed-by: default avatarArun R Murthy <arun.r.murthy@intel.com>
    Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20240729144458.2763667-1-imre.deak@intel.com
    aa705f7e
intel_dp_link_training.c 60.4 KB