• Edward Cree's avatar
    sfc_ef100: read Design Parameters at probe time · adcfc348
    Edward Cree authored
    Several parts of the EF100 architecture are parameterised (to allow
     varying capabilities on FPGAs according to resource constraints), and
     these parameters are exposed to the driver through a TLV-encoded
     region of the BAR.
    For the most part we either don't care about these values at all or
     just need to sanity-check them against the driver's assumptions, but
     there are a number of TSO limits which we record so that we will be
     able to check against them in the TX path when handling GSO skbs.
    Signed-off-by: default avatarEdward Cree <ecree@solarflare.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    adcfc348
ef100_nic.c 23.5 KB