Fix wrong "port" calculations in pdc202xx_{configure_piomode,set_dmamode}()
They were broken for all configurations except one (master device on primary
channel, no other devices) and as a result device settings + PIO/DMA timings
were being programmed into the wrong PCI registers.  This could result in
a large variety of problems including data corruption, hangs etc. (depending
on devices used and your luck :-).

  ap->port_no   ap->devno   used PCI registers   correct PCI registers
            0           0            0x60-0x62               0x60-0x62
            0           1            0x62-0x64               0x64-0x66
            1           0            0x64-0x66               0x68-0x6a
            1           1            0x66-0x68               0x6c-0x6e

Also forward port recent fixes from drivers/ide pdc202xx_old driver:

* fix XFER_MW_DMA0 timings (they were overclocked, use the official ones)

* fix bitmasks for clearing bits of register B:

  - when programming DMA mode bit 0x10 of register B was cleared which
    resulted in overclocked PIO timing setting (iff PIO0 was used)

  - when programming PIO mode bits 0x18 weren't cleared so suboptimal
    timings were used for PIO1-4 if PIO0 was previously set (bit 0x10)
    and for PIO0/3/4 if PIO1/2 was previously set (bit 0x08)

and finally bump driver version.
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>