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Chew, Chiau Ee authored
The Intel LPSS SPI private register bits have to be restored when system resume from S3 suspend. Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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