• Borun Fu's avatar
    drm/i915: Power gating display wells during i915_pm_suspend · b04c5bd6
    Borun Fu authored
    On VLV, after i915_pm_suspend display power wells are staying
    power ungated. So, after initiating mem sleep "echo mem > /sys/power/state"
    Display is staing D0 State. There might be better way/place to power gate
    these wells. Also, we need to make sure that if wells are power gated due to
    DPMS OFF sequence, they need not be turned off by i915_pm_suspend again.
    
    v2: Extracted helper for intel_crtc_disable and power gating CRTC power wells.
    [Daniel]
    
    Cc: Imre Deak <imre.deak@intel.com>
    Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
    Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
    Cc: Jani Nikula <jani.nikula@linux.intel.com>
    Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848
    Signed-off-by: default avatarBorun Fu <borun.fu@intel.com>
    Signed-off-by: default avatarSagar Kamble <sagar.a.kamble@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    b04c5bd6
intel_display.c 366 KB