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Sudeep Holla authored
The GICv2 CPU interface registers span across 8K, not 4K as indicated in the DT. Only the GICC_DIR register is located after the initial 4K boundary, leaving a functional system but without support for separately EOI'ing and deactivating interrupts. After this change the system supports split priority drop and interrupt deactivation. This patch is based on similar one from Christoffer Dall: commit 368400e2 ("ARM: dts: vexpress: Support GICC_DIR operations") Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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