• Suzuki Poulose's avatar
    powerpc/47x: Kernel support for KEXEC · 68343020
    Suzuki Poulose authored
    This patch adds support for creating 1:1 mapping for the PPC_47x during
    a KEXEC. The implementation is similar to that of the PPC440x which is
    described here :
    
    	http://patchwork.ozlabs.org/patch/104323/
    
    PPC_47x MMU :
    
    The 47x uses Unified TLB 1024 entries, with 4-way associative mapping
    (4 x 256 entries). The index to be used is calculated by the MMU by
    hashing the PID, EPN and TS. The software can choose to specify the way
    by setting bit 0(enable way select) and the way in bits 1-2 in the TLB
    Word 0.
    
    Implementation:
    
    The patch erases all the UTLB entries which includes the tlb covering
    the mapping for our code. The shadow TLB caches the mapping for the
    running code which helps us to continue the execution until we do
    isync/rfi. We then create a tmp mapping for the current code in the
    other address space (TS) and switch to it.
    
    Then we create a 1:1 mapping(EPN=RPN) for 0-2GiB in the original
    address space and switch to the new mapping.
    
    TODO: Add SMP support.
    Signed-off-by: default avatarSuzuki K. Poulose <suzuki@in.ibm.com>
    Signed-off-by: default avatarJosh Boyer <jwboyer@gmail.com>
    68343020
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