• Julius Werner's avatar
    clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused · bf92384b
    Julius Werner authored
    Rockchip RK3399 PLLs can be used in two separate modes: integral and
    fractional. We can select between these two modes with the unambiguously
    named DSMPD bit.
    
    During boot, we check all PLL settings to confirm that they match our
    PLL table for that frequency, and reinitialize the PLLs where they
    don't. The settings checked for this include the fractional divider
    field that is only used in fractional mode, even if we're in integral
    mode (DSMPD = 1) and that field has no effect.
    
    This patch changes the check to only compare the fractional divider if
    we're actually in fractional mode. This way, we won't reinitialize the
    PLL in cases where there's absolutely no reason for that, which may
    avoid glitching child clocks that should better not be glitched (e.g.
    PWM regulators).
    Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
    
    [cloned the fix to the pretty similar rk3036 pll]
    Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
    bf92384b
clk-pll.c 27.7 KB