• Vignesh Balasubramanian's avatar
    x86/elf: Add a new FPU buffer layout info to x86 core files · ba386777
    Vignesh Balasubramanian authored
    Add a new .note section containing type, size, offset and flags of every
    xfeature that is present.
    
    This information will be used by debuggers to understand the XSAVE layout of
    the machine where the core file has been dumped, and to read XSAVE registers,
    especially during cross-platform debugging.
    
    The XSAVE layouts of modern AMD and Intel CPUs differ, especially since
    Memory Protection Keys and the AVX-512 features have been inculcated into
    the AMD CPUs.
    
    Since AMD never adopted (and hence never left room in the XSAVE layout for)
    the Intel MPX feature, tools like GDB had assumed a fixed XSAVE layout
    matching that of Intel (based on the XCR0 mask).
    
    Hence, core dumps from AMD CPUs didn't match the known size for the XCR0 mask.
    This resulted in GDB and other tools not being able to access the values of
    the AVX-512 and PKRU registers on AMD CPUs.
    
    To solve this, an interim solution has been accepted into GDB, and is already
    a part of GDB 14, see
    
      https://sourceware.org/pipermail/gdb-patches/2023-March/198081.html.
    
    But it depends on heuristics based on the total XSAVE register set size
    and the XCR0 mask to infer the layouts of the various register blocks
    for core dumps, and hence, is not a foolproof mechanism to determine the
    layout of the XSAVE area.
    
    Therefore, add a new core dump note in order to allow GDB/LLDB and other
    relevant tools to determine the layout of the XSAVE area of the machine where
    the corefile was dumped.
    
    The new core dump note (which is being proposed as a per-process .note
    section), NT_X86_XSAVE_LAYOUT (0x205) contains an array of structures.
    
    Each structure describes an individual extended feature containing
    offset, size and flags in this format:
    
      struct x86_xfeat_component {
             u32 type;
             u32 size;
             u32 offset;
             u32 flags;
      };
    
    and in an independent manner, allowing for future extensions without depending
    on hw arch specifics like CPUID etc.
    
      [ bp: Massage commit message, zap trailing whitespace. ]
    Co-developed-by: default avatarJini Susan George <jinisusan.george@amd.com>
    Signed-off-by: default avatarJini Susan George <jinisusan.george@amd.com>
    Co-developed-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
    Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
    Signed-off-by: default avatarVignesh Balasubramanian <vigbalas@amd.com>
    Link: https://lore.kernel.org/r/20240725161017.112111-2-vigbalas@amd.com
    ba386777
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