• Arjun Vynipadath's avatar
    cxgb4: Update IngPad and IngPack values · bb58d079
    Arjun Vynipadath authored
    We are using the smallest padding boundary (8 bytes), which isn't
    smaller than the Memory Controller Read/Write Size
    
    We get best performance in 100G when the Packing Boundary is a multiple
    of the Maximum Payload Size. Its related to inefficient chopping of DMA
    packets by PCIe, that causes more overhead on bus. So driver is helping
    by making the starting address alignment to be MPS size.
    
    We will try to determine PCIE MaxPayloadSize capabiltiy  and set
    IngPackBoundary based on this value. If cache line size is greater than
    MPS or determinig MPS fails, we will use cache line size to determine
    IngPackBoundary(as before).
    Signed-off-by: default avatarArjun Vynipadath <arjun@chelsio.com>
    Signed-off-by: default avatarCasey Leedom <leedom@chelsio.com>
    Signed-off-by: default avatarGanesh Goudar <ganeshgr@chelsio.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    bb58d079
t4_values.h 5.44 KB