• Kevin Cernekee's avatar
    IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers · 5f7f0317
    Kevin Cernekee authored
    This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
    it has the following characteristics:
    
     - 64 to 160+ level IRQs
     - Atomic set/clear registers
     - Reasonably predictable register layout (N status words, then N
       mask status words, then N mask set words, then N mask clear words)
     - SMP affinity supported on most systems
     - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
    
    This driver registers one IRQ domain and one IRQ chip to cover all
    instances of the block.  Up to 4 instances of the block may appear, as
    it supports 4-way IRQ affinity on BCM7435.
    
    The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
    is used instead.  So this driver is primarily intended for MIPS STB chips.
    Signed-off-by: default avatarKevin Cernekee <cernekee@gmail.com>
    Cc: f.fainelli@gmail.com
    Cc: jaedon.shin@gmail.com
    Cc: abrestic@chromium.org
    Cc: tglx@linutronix.de
    Cc: jason@lakedaemon.net
    Cc: jogo@openwrt.org
    Cc: arnd@arndb.de
    Cc: computersforpeace@gmail.com
    Cc: linux-mips@linux-mips.org
    Cc: devicetree@vger.kernel.org
    Cc: linux-kernel@vger.kernel.org
    Patchwork: https://patchwork.linux-mips.org/patch/8844/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    5f7f0317
brcm,bcm7038-l1-intc.txt 1.86 KB