• Chris Wilson's avatar
    drm/i915: Evict CS TLBs between batches · c4d69da1
    Chris Wilson authored
    Running igt, I was encountering the invalid TLB bug on my 845g, despite
    that it was using the CS workaround. Examining the w/a buffer in the
    error state, showed that the copy from the user batch into the
    workaround itself was suffering from the invalid TLB bug (the first
    cacheline was broken with the first two words reversed). Time to try a
    fresh approach. This extends the workaround to write into each page of
    our scratch buffer in order to overflow the TLB and evict the invalid
    entries. This could be refined to only do so after we update the GTT,
    but for simplicity, we do it before each batch.
    
    I suspect this supersedes our current workaround, but for safety keep
    doing both.
    
    v2: The magic number shall be 2.
    
    This doesn't conclusively prove that it is the mythical TLB bug we've
    been trying to workaround for so long, that it requires touching a number
    of pages to prevent the corruption indicates to me that it is TLB
    related, but the corruption (the reversed cacheline) is more subtle than
    a TLB bug, where we would expect it to read the wrong page entirely.
    
    Oh well, it prevents a reliable hang for me and so probably for others
    as well.
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
    Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
    Cc: stable@vger.kernel.org
    Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
    c4d69da1
intel_ringbuffer.c 69.5 KB