• Nishanth Aravamudan's avatar
    NVMe: default to 4k device page size · c5c9f25b
    Nishanth Aravamudan authored
    We received a bug report recently when DDW (64-bit direct DMA on Power)
    is not enabled for NVMe devices. In that case, we fall back to 32-bit
    DMA via the IOMMU, which is always done via 4K TCEs (Translation Control
    Entries).
    
    The NVMe device driver, though, assumes that the DMA alignment for the
    PRP entries will match the device's page size, and that the DMA aligment
    matches the kernel's page aligment. On Power, the the IOMMU page size,
    as mentioned above, can be 4K, while the device can have a page size of
    8K, while the kernel has a page size of 64K. This eventually trips the
    BUG_ON in nvme_setup_prps(), as we have a 'dma_len' that is a multiple
    of 4K but not 8K (e.g., 0xF000).
    
    In this particular case of page sizes, we clearly want to use the
    IOMMU's page size in the driver. And generally, the NVMe driver in this
    function should be using the IOMMU's page size for the default device
    page size, rather than the kernel's page size. There is not currently an
    API to obtain the IOMMU's page size across all architectures and in the
    interest of a stop-gap fix to this functional issue, default the NVMe
    device page size to 4K, with the intent of adding such an API and
    implementation across all architectures in the next merge window.
    
    With the functionally equivalent v3 of this patch, our hardware test
    exerciser survives when using 32-bit DMA; without the patch, the kernel
    will BUG within a few minutes.
    
    Signed-off-by: Nishanth Aravamudan <nacc at linux.vnet.ibm.com>
    Signed-off-by: default avatarJens Axboe <axboe@fb.com>
    c5c9f25b
pci.c 85.9 KB