• Catalin Marinas's avatar
    [ARM] 4582/2: Add support for the common VFP subarchitecture · c98929c0
    Catalin Marinas authored
    This patch allows the VFP support code to run correctly on CPUs
    compatible with the common VFP subarchitecture specification (Appendix
    B in the ARM ARM v7-A and v7-R edition). It implements support for VFP
    subarchitecture 2 while being backwards compatible with
    subarchitecture 1.
    
    On VFP subarchitecture 1, the arithmetic exceptions are asynchronous
    (or imprecise as described in the old ARM ARM) unless the FPSCR.IXE
    bit is 1. The exceptional instructions can be read from FPINST and
    FPINST2 registers. With VFP subarchitecture 2, the arithmetic
    exceptions can also be synchronous and marked by the FPEXC.DEX bit
    (the FPEXC.EX bit is cleared). CPUs implementing the synchronous
    arithmetic exceptions don't have the FPINST and FPINST2 registers and
    accessing them would trigger and undefined exception.
    
    Note that FPEXC.EX bit has an additional meaning on subarchitecture 1
    - if it isn't set, there is no additional information in FPINST and
    FPINST2 that needs to be saved at context switch or when lazy-loading
    the VFP state of a different thread.
    
    The patch also removes the clearing of the cumulative exception flags in
    FPSCR when additional exceptions were raised. It is up to the user
    application to clear these bits.
    Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    c98929c0
vfphw.S 6.28 KB