• Lendacky, Thomas's avatar
    amd-xgbe: Optimize DMA channel interrupt enablement · caa575af
    Lendacky, Thomas authored
    Currently whenever the driver needs to enable or disable interrupts for
    a DMA channel it reads the interrupt enable register (IER), updates the
    value and then writes the new value back to the IER. Since the hardware
    does not change the IER, software can track this value and elimiate the
    need to read it each time.
    
    Add the IER value to the channel related data structure and use that as
    the base for enabling and disabling interrupts, thus removing the need
    for the MMIO read.
    Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    caa575af
xgbe-dev.c 95.6 KB