• Markos Chandras's avatar
    MIPS: c-r4k: Fix cache flushing for MT cores · cccf34e9
    Markos Chandras authored
    MT_SMP is not the only SMP option for MT cores. The MT_SMP option
    allows more than one VPE per core to appear as a secondary CPU in the
    system. Because of how CM works, it propagates the address-based
    cache ops to the secondary cores but not the index-based ones.
    Because of that, the code does not use IPIs to flush the L1 caches on
    secondary cores because the CM would have done that already. However,
    the CM functionality is independent of the type of SMP kernel so even in
    non-MT kernels, IPIs are not necessary. As a result of which, we change
    the conditional to depend on the CM presence. Moreover, since VPEs on
    the same core share the same L1 caches, there is no need to send an
    IPI on all of them so we calculate a suitable cpumask with only one
    VPE per core.
    Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
    Cc: <stable@vger.kernel.org> # 3.15+
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/10654/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    cccf34e9
c-r4k.c 45.8 KB