• Aneesh Kumar K.V's avatar
    powerpc/mm/radix: Optimise Page Walk Cache flush · cf4f08be
    Aneesh Kumar K.V authored
    Currently we implement flushing of the page walk cache (PWC) by calling
    _tlbiel_pid() with a RIC (Radix Invalidation Control) value of 1 which says to
    only flush the PWC.
    
    But _tlbiel_pid() loops over each set (congruence class) of the TLB, which is
    not necessary when we're just flushing the PWC.
    
    In fact the set argument is ignored for a PWC flush, so essentially we're just
    flushing the PWC 127 extra times for no benefit.
    
    Fix it by adding tlbiel_pwc() which just does a single flush of the PWC.
    Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
    [mpe: Split out of combined patch, drop _ in name, rewrite change log]
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    cf4f08be
tlb-radix.c 12 KB