According to Bspec, the voltage level for 480MHz is to be set as 1
instead of 2.

BSpec: 49208

Fixes: 06f1b06d ("drm/i915/display: Add 480 MHz CDCLK steps for RPL-U")

v2: rebase
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230529060747.3972259-1-chaitanya.kumar.borah@intel.com
(cherry picked from commit 5a3c46b8)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>