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Swapnil Jakhade authored
Add PHY registers for single link DP in array format to simplify code and to improve readability. This supports already supported frequencies for DP of 19.2MHz and 25MHz. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-6-sjakhade@cadence.com Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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