• Tvrtko Ursulin's avatar
    drm/i915: Show timeline dependencies for debug · da7ac715
    Tvrtko Ursulin authored
    Include the signalers each request in the timeline is waiting on, as a
    means to try and identify the cause of a stall. This can be quite
    verbose, even as for now we only show each request in the timeline and
    its immediate antecedents.
    
    This generates output like:
    
    Timeline 886: { count 1, ready: 0, inflight: 0, seqno: { current: 664, last: 666 }, engine: rcs0 }
      U 886:29a-  prio=0 @ 134ms: gem_exec_parall<4621>
        U bc1:27a-  prio=0 @ 134ms: gem_exec_parall[4917]
    Timeline 825: { count 1, ready: 0, inflight: 0, seqno: { current: 802, last: 804 }, engine: vcs0 }
      U 825:324  prio=0 @ 107ms: gem_exec_parall<4518>
        U b75:140-  prio=0 @ 110ms: gem_exec_parall<5486>
    Timeline b46: { count 1, ready: 0, inflight: 0, seqno: { current: 782, last: 784 }, engine: vcs0 }
      U b46:310-  prio=0 @ 70ms: gem_exec_parall<5428>
        U c11:170-  prio=0 @ 70ms: gem_exec_parall[5501]
    Timeline 96b: { count 1, ready: 0, inflight: 0, seqno: { current: 632, last: 634 }, engine: vcs0 }
      U 96b:27a-  prio=0 @ 67ms: gem_exec_parall<4878>
        U b75:19e-  prio=0 @ 67ms: gem_exec_parall<5486>
    Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
    Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Link: https://patchwork.freedesktop.org/patch/msgid/20201119165616.10834-6-chris@chris-wilson.co.uk
    da7ac715
i915_scheduler.c 14.9 KB