• Pavana Sharma's avatar
    net: dsa: mv88e6xxx: add support for mv88e6393x family · de776d0d
    Pavana Sharma authored
    The Marvell 88E6393X device is a single-chip integration of a 11-port
    Ethernet switch with eight integrated Gigabit Ethernet (GbE)
    transceivers and three 10-Gigabit interfaces.
    
    This patch adds functionalities specific to mv88e6393x family (88E6393X,
    88E6193X and 88E6191X).
    
    The main differences between previous devices and this one are:
    - port 0 can be a SERDES port
    - all SERDESes are one-lane, eg. no XAUI nor RXAUI
    - on the other hand the SERDESes can do USXGMII, 10GBASER and 5GBASER
      (on 6191X only one SERDES is capable of more than 1g; USXGMII is not
      yet supported with this change)
    - Port Policy CTL register is changed to Port Policy MGMT CTL register,
      via which several more registers can be accessed indirectly
    - egress monitor port is configured differently
    - ingress monitor/CPU/mirror ports are configured differently and can be
      configured per port (ie. each port can have different ingress monitor
      port, for example)
    - port speed AltBit works differently than previously
    - PHY registers can be also accessed via MDIO address 0x18 and 0x19
      (on previous devices they could be accessed only via Global 2 offsets
       0x18 and 0x19, which means two indirections; this feature is not yet
       leveraged with thiis commit)
    Co-developed-by: default avatarAshkan Boldaji <ashkan.boldaji@digi.com>
    Signed-off-by: default avatarAshkan Boldaji <ashkan.boldaji@digi.com>
    Signed-off-by: default avatarPavana Sharma <pavana.sharma@digi.com>
    Co-developed-by: default avatarMarek Behún <kabel@kernel.org>
    Signed-off-by: default avatarMarek Behún <kabel@kernel.org>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    de776d0d
serdes.h 9.09 KB