This is more conservative in general, and so applies to multiple
controllers.  Specifically it attempts to address irq-related issues
on the Intel ICH5/6 hardware.  On Intel ICH5/6, the BMDMA 'interrupt'
status bit will be set even on non-DMA commands, which software
(and I) did not expect.

This change clears pending interrupts once upon initialization,
and then each time ata_irq_on() is called.