There was a discussion a long time ago about how safe the bit operations
were as well as recently.

set_bit/clear_bit are not safe on x86 UP, nor are they safe on other
architectures. It's also unclear from the UHCI spec if the HC's are safe
with respect to atomic updates to the status field.

This patch ditches all of the uses of set_bit and clear_bit and changes
the algorithm that depended on it.

The FSBR timeout algorithm would reenable FSBR for transfers when they
started making progress again. So instead of trying for this best case,
we convert the transfer over to depth first from the standard breadth
first. To make sure the transfer doesn't hog all of the bandwidth, every
5th TD is left in breadth first mode. This will ensure other transfers
get some bandwidth.

It's not perfect, but I think it's a good compromise.

Note: td->info is read only by the HC, so we can touch it whenever we
want.