• Chris Wilson's avatar
    drm/i915: Keep timeline HWSP allocated until idle across the system · ebece753
    Chris Wilson authored
    In preparation for enabling HW semaphores, we need to keep in flight
    timeline HWSP alive until its use across entire system has completed,
    as any other timeline active on the GPU may still refer back to the
    already retired timeline. We both have to delay recycling available
    cachelines and unpinning old HWSP until the next idle point.
    
    An easy option would be to simply keep all used HWSP until the system as
    a whole was idle, i.e. we could release them all at once on parking.
    However, on a busy system, we may never see a global idle point,
    essentially meaning the resource will be leaked until we are forced to
    do a GC pass. We already employ a fine-grained idle detection mechanism
    for vma, which we can reuse here so that each cacheline can be freed
    immediately after the last request using it is retired.
    
    v3: Keep track of the activity of each cacheline.
    v4: cacheline_free() on canceling the seqno tracking
    v5: Finally with a testcase to exercise wraparound
    v6: Pack cacheline into empty bits of page-aligned vaddr
    v7: Use i915_utils to hide the pointer casting around bit manipulation
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20190301170901.8340-2-chris@chris-wilson.co.uk
    ebece753
i915_timeline.c 18.8 KB