Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This
is a test chip for their upcoming JH7110 SoC.

The CPU and cache data is based on the device tree in the vendor u-boot
port.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>