• Andi Kleen's avatar
    x86, mce: implement new status bits · ed7290d0
    Andi Kleen authored
    The x86 architecture recently added some new machine check status bits:
    S(ignalled) and AR (Action-Required). Signalled allows to check
    if a specific event caused an exception or was just logged through CMCI.
    AR allows the kernel to decide if an event needs immediate action
    or can be delayed or ignored.
    
    Implement support for these new status bits. mce_severity() uses
    the new bits to grade the machine check correctly and decide what
    to do. The exception handler uses AR to decide to kill or not.
    The S bit is used to separate events between the poll/CMCI handler
    and the exception handler.
    
    Classical UC always leads to panic. That was true before anyways
    because the existing CPUs always passed a PCC with it.
    
    Also corrects the rules whether to kill in user or kernel context
    and how to handle missing RIPV.
    
    The machine check handler largely uses the mce-severity grading
    engine now instead of making its own decisions. This means the logic
    is centralized in one place.  This is useful because it has to be
    evaluated multiple times.
    
    v2: Some rule fixes; Add AO events
    Fix RIPV, RIPV|EIPV order (Ying Huang)
    Fix UCNA with AR=1 message (Ying Huang)
    Add comment about panicing in m_c_p.
    Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
    Signed-off-by: default avatarHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
    Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
    ed7290d0
mce-internal.h 261 Bytes