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Swapnil Jakhade authored
Add multilink DP configuration support for 100MHz reference clock rate. This is the only clock rate supported currently for multilink PHY configurations. Also, add PCIe + DP multiprotocol multilink register configuration sequences for 100MHz refclk with no SSC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20230418173157.25607-4-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>
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