The K3 AM64x SoC family has a revised R5F sub-system and contains a
subset of the R5F clusters present on J721E SoCs. The K3 AM64x SoCs
only have two dual-core Arm R5F clusters/subsystems with 2 R5F cores
each present within the MAIN voltage domain (MAIN_R5FSS0 & MAIN_R5FSS1).

The revised IP has the following distinct features:
 1. The R5FSS IP supports a new "Single-CPU" mode instead of the LockStep
    mode on existing SoCs (AM65x, J721E or J7200). This mode is similar
    to LockStep-mode on J7200 SoCs in terms of TCM usage without the
    fault-tolerant safety feature provided by the LockStep mode.

    The Core1 TCMs are combined with the Core0 TCMs effectively doubling
    the amount of TCMs available in Single-CPU mode. The LockStep-mode
    on previous AM65x and J721E SoCs could only use the Core0 TCMs. These
    combined TCMs appear contiguous at the respective Core0 TCM addresses.
    The code though is executed only on a single CPU (on Core0), and as
    such, requires the halt signal to be programmed only for Core0, while
    the resets need to be managed for both the cores.

 2. TCMs are auto-initialized during module power-up, and the behavior
    is programmable through a MMR bit. This feature is the same as on
    the recent J7200 SoCs.

Extend the support to these clusters in the K3 R5F remoteproc driver
using AM64x specific compatibles. New TI-SCI flags and a unique cluster
mode are also needed for the cluster mode detection on these SoCs. The
reset assert and deassert sequence of both the cores in Single-CPU mode
is agnostic of the order, so the same LockStep reset and release sequences
are re-used.

The integration of these clusters is very much similar to existing SoCs
otherwise.
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20210327143117.1840-3-s-anna@ti.comSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>