This reduces the size of struct skl_wm_level from 6 to 4, which
reduces the size of struct skl_plane_wm from 104 to 70, which reduces
the size of struct skl_pipe_wm from 524 to 356. A reduction of 168
padding bytes per pipe. This will increase even more the next time we
bump I915_MAX_PLANES.

v2: Paste the pahole output provided by Lucas:

$ pahole -s -C skl_wm_level drivers/gpu/drm/i915/i915.o
struct skl_wm_level {
        bool                       plane_en;             /*     0     1 */

        /* XXX 1 byte hole, try to pack */

        uint16_t                   plane_res_b;          /*     2     2 */
        uint8_t                    plane_res_l;          /*     4     1 */

        /* size: 6, cachelines: 1, members: 3 */
        /* sum members: 4, holes: 1, sum holes: 1 */
        /* padding: 1 */
        /* last cacheline: 6 bytes */
};
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181016220133.26991-3-paulo.r.zanoni@intel.com