• Matt Roper's avatar
    drm/i915/xelpg: Add multicast steering · f32898c9
    Matt Roper authored
    MTL's graphics IP (Xe_LPG) once again changes the multicast register
    types and steering details.  Key changes from past platforms:
     * The number of instances of some MCR types (NODE, OAAL2, and GAM) vary
       according to the MTL subplatform and cannot be read from fuse
       registers.  However steering to instance #0 will always provided a
       non-terminated value, so we can lump these all into a single
       "instance0" table.
     * The MCR steering register (and its bitfields) has changed.
    
    Unlike past platforms, we will be explicitly steering all types of MCR
    accesses, including those for "SLICE" and "DSS" ranges; we no longer
    rely on implicit steering.  On previous platforms, various
    hardware/firmware agents that needed to access registers typically had
    their own steering control registers, allowing them to perform multicast
    steering without clobbering the CPU/kernel steering.  Starting with MTL,
    more of these agents now share a single steering register (0xFD4) and it
    is no longer safe for us to assume that the value will remain unchanged
    from how we initialized it during startup.  There is also a slight
    chance of race conditions between the driver and a hardware/firmware
    agent, so the hardware provides a semaphore register that can be used to
    coordinate access to the steering register.  Support for the semaphore
    register will be introduced in a future patch.
    
    v2:
     - Use Xe_LPG terminology instead of "MTL 3D" since it's the IP version
       we're matching on now rather than the platform.
     - Don't combine l3bank and mslice masks into a union.  It's not related
       to the other changes here and we might still need both of them on
       some future platform.
     - Separate debug dumping of steering settings to a separate helper
       function.  (Tvrtko)
     - Update debug dumping to include DSS ranges (and future-proof it so
       that any new ranges added on future platforms will also be dumped).
     - Restore MULTICAST bit at the end of rw_with_mcr_steering_fw() if we
       cleared it.  Also force the MULTICAST bit to true at the beginning of
       multicast writes just to be safe.  (Bala)
    
    Bspec: 67788, 67112
    Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
    Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
    Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
    Reviewed-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20221014230239.1023689-14-matthew.d.roper@intel.com
    f32898c9
i915_pci.c 36.5 KB