• Chris Zhong's avatar
    ASoC: rockchip: correct the spdif clk · 46dd2e28
    Chris Zhong authored
    The spdif mclk should be 128 times of sample rate, and there is a
    internal divider, the real rate of spdif mclk is mclk / (div + 1).
    Hence, the original driver always get the good frequency for
    48000/96000/44100/192000. But for 32000, the mclk is incorrect,
    it should be 32000*128, but get 48000*128. Do not use the internal
    divider here, just set all mclk to 128 * sample rate directly.
    Signed-off-by: default avatarChris Zhong <zyw@rock-chips.com>
    Signed-off-by: default avatarMark Brown <broonie@kernel.org>
    46dd2e28
rockchip_spdif.c 9.28 KB