• Florian Fainelli's avatar
    soc: bcm: brcmstb: Add missing DDR MEMC compatible strings · a334e45d
    Florian Fainelli authored
    We would not be matching the following chip/compatible strings
    combinations, which would lead to not setting the warm boot flag
    correctly, fix that:
    
        7260A0/B0: brcm,brcmstb-memc-ddr-rev-b.2.1
        7255A0: brcm,brcmstb-memc-ddr-rev-b.2.3
        7278Bx: brcm,brcmstb-memc-ddr-rev-b.3.1
    
    The B2.1 core (which is in 7260 A0 and B0) doesn't have the
    SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL setup in the memsys init code, nor
    does it have the warm boot flag re-definition on entry. Those changes
    were for B2.2 and later MEMSYS cores. Fall back to the previous S2/S3
    entry method for these specific chips.
    
    Fixes: 0b741b82 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)")
    Reviewed-by: default avatarRob Herring <robh@kernel.org>
    Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
    a334e45d
pm-arm.c 19.6 KB