Add the DT nodes for the ICSSG0, ICSSG1 and ICSSG2 processor subsystems
that are present on the K3 AM65x SoCs. The three ICSSGs are identical
to each other for the most part, with the ICSSG2 supporting slightly
enhanced features for supporting SGMII PRU Ethernet. Each ICSSG instance
is represented by a PRUSS subsystem node. These nodes are enabled by
default.

The ICSSGs on K3 AM65x SoCs are super-sets of the PRUSS on the AM57xx/
6AK2G SoCs except for larger Shared Data RAM and the lack of a PRU-ICSS
crossbar. They include two auxiliary PRU cores called RTUs and few other
additional sub-modules. The interrupt integration is also different on
the K3 AM65x SoCs and are propagated through various SoC-level Interrupt
Router and Interrupt Aggregator blocks. The AM65x SR2.0 SoCs have a
revised ICSSG IP that is based off the subsequent IP used on J721E SoCs,
and has two new auxiliary PRU cores called Tx_PRUs. The Tx_PRUs have 6 KB
of IRAMs and leverage the same host interrupts as the regular PRU cores.
The Broadside (BS) RAM within each core is also sized differently w.r.t
SR1.0.

The ICSSG subsystem node contains the entire address space. The various
sub-modules of the ICSSG are represented as individual child nodes (so
platform devices themselves) of the PRUSS subsystem node. These include
the various PRU cores and the interrupt controller. All the Data RAMs
are represented within a child node of its own named 'memories' without
any compatible. The Real Time Media Independent Interface controllers
(MII_RT and MII_G_RT), and the CFG sub-module are represented as syscon
nodes. The ICSSG CFG module has clock muxes for IEP clock and CORE clock,
these clk nodes are added under the CFG child node 'clocks'. The default
parents for these mux clocks are also assigned.

The DT nodes use all standard properties. The regs property in the
PRU/RTU/Tx_PRU nodes define the addresses for the Instruction RAM, the
Debug and Control sub-modules for that PRU core. The firmware for each
PRU/RTU/Tx_PRU core is defined through a 'firmware-name' property.

The default names for the firmware images for each PRU, RTU and Tx_PRU
cores are defined as follows (these can be adjusted either in derivative
board dts files or through sysfs at runtime if required):
 ICSSG0 PRU0 Core    : am65x-pru0_0-fw   ; PRU1 Core    : am65x-pru0_1-fw
 ICSSG0 RTU0 Core    : am65x-rtu0_0-fw   ; RTU1 Core    : am65x-rtu0_1-fw
 ICSSG0 Tx_PRU0 Core : am65x-txpru0_0-fw ; Tx_PRU1 Core : am65x-txpru0_1-fw
 ICSSG1 PRU0 Core    : am65x-pru1_0-fw   ; PRU1 Core    : am65x-pru1_1-fw
 ICSSG1 RTU0 Core    : am65x-rtu1_0-fw   ; RTU1 Core    : am65x-rtu1_1-fw
 ICSSG1 Tx_PRU0 Core : am65x-txpru1_0-fw ; Tx_PRU1 Core : am65x-txpru1_1-fw
 ICSSG2 PRU0 Core    : am65x-pru2_0-fw   ; PRU1 Core    : am65x-pru2_1-fw
 ICSSG2 RTU0 Core    : am65x-rtu2_0-fw   ; RTU1 Core    : am65x-rtu2_1-fw
 ICSSG2 Tx_PRU0 Core : am65x-txpru2_0-fw ; Tx_PRU1 Core : am65x-txpru2_1-fw

Note:
1. The ICSSG nodes are all added as per the SR2.0 device. Any sub-module IP
   differences need to be handled within the driver using SoC device match
   logic or separate dts/overlay files (if needs to be supported) with the
   Tx_PRU nodes expected to be disabled at the minimum.
2. The ICSSG INTC on AM65x SoCs share 5, 6, 7 host interrupts with other
   processors, so use the 'ti,irqs-reserved' property in derivative board
   dts files _if_ any of them should not be handled by the host OS.
3. There are few more sub-modules like the Industrial Ethernet Peripherals
   (IEPs), MDIO, PWM, UART that do not have bindings and so will be added
   in the future.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20210304160712.8452-2-s-anna@ti.com