• Dmitry Osipenko's avatar
    drm/tegra: dc: Don't set PLL clock to 0Hz · f8fb97c9
    Dmitry Osipenko authored
    RGB output doesn't allow to change parent clock rate of the display and
    PCLK rate is set to 0Hz in this case. The tegra_dc_commit_state() shall
    not set the display clock to 0Hz since this change propagates to the
    parent clock. The DISP clock is defined as a NODIV clock by the tegra-clk
    driver and all NODIV clocks use the CLK_SET_RATE_PARENT flag.
    
    This bug stayed unnoticed because by default PLLP is used as the parent
    clock for the display controller and PLLP silently skips the erroneous 0Hz
    rate changes because it always has active child clocks that don't permit
    rate changes. The PLLP isn't acceptable for some devices that we want to
    upstream (like Samsung Galaxy Tab and ASUS TF700T) due to a display panel
    clock rate requirements that can't be fulfilled by using PLLP and then the
    bug pops up in this case since parent clock is set to 0Hz, killing the
    display output.
    
    Don't touch DC clock if pclk=0 in order to fix the problem.
    Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
    Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
    f8fb97c9
dc.c 71.4 KB