• Caesar Wang's avatar
    ARM: rockchip: fix the CPU soft reset · fe4407c0
    Caesar Wang authored
    We need different orderings when turning a core on and turning a core
    off.  In one case we need to assert reset before turning power off.
    In ther other case we need to turn power on and the deassert reset.
    
    In general, the correct flow is:
    
    CPU off:
        reset_control_assert
        regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd))
        wait_for_power_domain_to_turn_off
    CPU on:
        regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0)
        wait_for_power_domain_to_turn_on
        reset_control_deassert
    
    This is needed for stressing CPU up/down, as per:
        cd /sys/devices/system/cpu/
        for i in $(seq 10000); do
            echo "================= $i ============"
            for j in $(seq 100); do
                while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "000"" ]]
                    echo 0 > cpu1/online
                    echo 0 > cpu2/online
                    echo 0 > cpu3/online
                done
                while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "111" ]]; do
                    echo 1 > cpu1/online
                    echo 1 > cpu2/online
                    echo 1 > cpu3/online
                done
            done
        done
    
    The following is reproducable log:
        [34466.186812] PM: noirq suspend of devices complete after 0.669 msecs
        [34466.186824] Disabling non-boot CPUs ...
        [34466.187509] CPU1: shutdown
        [34466.188672] CPU2: shutdown
        [34473.736627] Kernel panic - not syncing:Watchdog detected hard LOCKUP on cpu 0
        .......
    or others similar log:
        .......
        [ 4072.454453] CPU1: shutdown
        [ 4072.504436] CPU2: shutdown
        [ 4072.554426] CPU3: shutdown
        [ 4072.577827] CPU1: Booted secondary processor
        [ 4072.582611] CPU2: Booted secondary processor
        <hang>
    
        Tested by cpu up/down scripts, the results told us need delay more time
    before write the sram. The wait time is affected by many aspects
    (e.g: cpu frequency, bootrom frequency, sram frequency, bus speed, ...).
    
        Although the cpus other than cpu0 will write the sram, the speedy is
    no the same as cpu0, if the cpu0 early wake up, perhaps the other cpus
    can't startup. As we know, the cpu0 can wake up when the cpu1/2/3 write
    the 'sram+4/8' and send the sev.
        Anyway.....
        At the moment, 1ms delay will be happy work for cpu up/down scripts test.
    Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
    Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
    Reviewed-by: default avatarKever Yang <kever.yang@rock-chips.com>
    Fixes: 3ee851e2 ("ARM: rockchip: add basic smp support for rk3288")
    Cc: stable@vger.kernel.org
    Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
    fe4407c0
platsmp.c 8.37 KB