Commit 006a851b authored by Steven J. Hill's avatar Steven J. Hill

MIPS: Add support for the 1074K core.

Signed-off-by: default avatarSteven J. Hill <sjhill@mips.com>
parent fea7a08a
...@@ -94,6 +94,7 @@ ...@@ -94,6 +94,7 @@
#define PRID_IMP_24KE 0x9600 #define PRID_IMP_24KE 0x9600
#define PRID_IMP_74K 0x9700 #define PRID_IMP_74K 0x9700
#define PRID_IMP_1004K 0x9900 #define PRID_IMP_1004K 0x9900
#define PRID_IMP_1074K 0x9a00
#define PRID_IMP_M14KC 0x9c00 #define PRID_IMP_M14KC 0x9c00
/* /*
......
...@@ -596,6 +596,8 @@ ...@@ -596,6 +596,8 @@
#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
#define MIPS_CONF7_WII (_ULCAST_(1) << 31) #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
......
...@@ -857,6 +857,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -857,6 +857,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
c->cputype = CPU_1004K; c->cputype = CPU_1004K;
__cpu_name[cpu] = "MIPS 1004Kc"; __cpu_name[cpu] = "MIPS 1004Kc";
break; break;
case PRID_IMP_1074K:
c->cputype = CPU_74K;
__cpu_name[cpu] = "MIPS 1074Kc";
break;
} }
spram_config(); spram_config();
......
...@@ -786,6 +786,25 @@ static inline void rm7k_erratum31(void) ...@@ -786,6 +786,25 @@ static inline void rm7k_erratum31(void)
} }
} }
static inline void alias_74k_erratum(struct cpuinfo_mips *c)
{
/*
* Early versions of the 74K do not update the cache tags on a
* vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
* aliases. In this case it is better to treat the cache as always
* having aliases.
*/
if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
c->dcache.flags |= MIPS_CACHE_VTAG;
if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
c->dcache.flags |= MIPS_CACHE_VTAG;
write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
}
}
static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way", static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
"3-way", "4-way", "5-way", "6-way", "7-way", "8-way" "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
}; };
...@@ -1056,6 +1075,8 @@ static void __cpuinit probe_pcache(void) ...@@ -1056,6 +1075,8 @@ static void __cpuinit probe_pcache(void)
case CPU_34K: case CPU_34K:
case CPU_74K: case CPU_74K:
case CPU_1004K: case CPU_1004K:
if (c->cputype == CPU_74K)
alias_74k_erratum(c);
if ((read_c0_config7() & (1 << 16))) { if ((read_c0_config7() & (1 << 16))) {
/* effectively physically indexed dcache, /* effectively physically indexed dcache,
thus no virtual aliases. */ thus no virtual aliases. */
......
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