Commit 03fa8fc9 authored by David S. Miller's avatar David S. Miller

Merge branch 'remove-virt_to_bus-drivers'

Jakub Kicinski says:

====================
net: remove non-Ethernet drivers using virt_to_bus()

Networking is currently the main offender in using virt_to_bus().
Frankly all the drivers which use it are super old and unlikely
to be used today. They are just an ongoing maintenance burden.

In other words this series is using virt_to_bus() as an excuse
to shed some old stuff. Having done the tree-wide dev_addr_set()
conversion recently I have limited sympathy for carrying dead
code.

Obviously please scream if any of these drivers _is_ in fact
still being used. Otherwise let's take the chance, we can always
apologize and revert if users show up later.

Also I should say thanks to everyone who contributed to this code!
The work continues to be appreciated although realistically in more
of a "history book" fashion...
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 95ccb041 865e2eb0
......@@ -1933,7 +1933,7 @@
...
255= /dev/umem/d15p15 15th partition of 16th board.
117 char COSA/SRP synchronous serial card
117 char [REMOVED] COSA/SRP synchronous serial card
0 = /dev/cosa0c0 1st board, 1st channel
1 = /dev/cosa0c1 1st board, 2nd channel
...
......
......@@ -17,7 +17,6 @@ Contents:
fddi/index
hamradio/index
qlogic/index
wan/index
wifi/index
wwan/index
......
.. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
Classic WAN Device Drivers
==========================
Contents:
.. toctree::
:maxdepth: 2
z8530book
.. only:: subproject and html
Indices
=======
* :ref:`genindex`
......@@ -5047,12 +5047,6 @@ S: Maintained
F: Documentation/hwmon/corsair-psu.rst
F: drivers/hwmon/corsair-psu.c
COSA/SRP SYNC SERIAL DRIVER
M: Jan "Yenya" Kasprzak <kas@fi.muni.cz>
S: Maintained
W: http://www.fi.muni.cz/~kas/cosa/
F: drivers/net/wan/cosa*
COUNTER SUBSYSTEM
M: William Breathitt Gray <vilhelm.gray@gmail.com>
L: linux-iio@vger.kernel.org
......@@ -8772,7 +8766,6 @@ F: kernel/time/timer_*.c
HIGH-SPEED SCC DRIVER FOR AX.25
L: linux-hams@vger.kernel.org
S: Orphan
F: drivers/net/hamradio/dmascc.c
F: drivers/net/hamradio/scc.c
HIGHPOINT ROCKETRAID 3xxx RAID DRIVER
......
......@@ -178,11 +178,8 @@ CONFIG_NETCONSOLE=m
CONFIG_ATM_TCP=m
CONFIG_ATM_LANAI=m
CONFIG_ATM_ENI=m
CONFIG_ATM_FIRESTREAM=m
CONFIG_ATM_ZATM=m
CONFIG_ATM_NICSTAR=m
CONFIG_ATM_IDT77252=m
CONFIG_ATM_HORIZON=m
CONFIG_ATM_IA=m
CONFIG_ATM_FORE200E=m
CONFIG_ATM_HE=m
......
......@@ -255,11 +255,8 @@ CONFIG_ARCNET_COM20020_CS=m
CONFIG_ATM_TCP=m
CONFIG_ATM_LANAI=m
CONFIG_ATM_ENI=m
CONFIG_ATM_FIRESTREAM=m
CONFIG_ATM_ZATM=m
CONFIG_ATM_NICSTAR=m
CONFIG_ATM_IDT77252=m
CONFIG_ATM_HORIZON=m
CONFIG_ATM_IA=m
CONFIG_ATM_FORE200E=m
CONFIG_ATM_HE=m
......
......@@ -146,36 +146,6 @@ config ATM_ENI_BURST_RX_2W
try this if you have disabled 4W and 8W bursts. Enabling 2W if 4W or
8W are also set may or may not improve throughput.
config ATM_FIRESTREAM
tristate "Fujitsu FireStream (FS50/FS155) "
depends on PCI && VIRT_TO_BUS
help
Driver for the Fujitsu FireStream 155 (MB86697) and
FireStream 50 (MB86695) ATM PCI chips.
To compile this driver as a module, choose M here: the module will
be called firestream.
config ATM_ZATM
tristate "ZeitNet ZN1221/ZN1225"
depends on PCI && VIRT_TO_BUS
help
Driver for the ZeitNet ZN1221 (MMF) and ZN1225 (UTP-5) 155 Mbps ATM
adapters.
To compile this driver as a module, choose M here: the module will
be called zatm.
config ATM_ZATM_DEBUG
bool "Enable extended debugging"
depends on ATM_ZATM
help
Extended debugging records various events and displays that list
when an inconsistency is detected. This mechanism is faster than
generally using printks, but still has some impact on performance.
Note that extended debugging may create certain race conditions
itself. Enable this ONLY if you suspect problems with the driver.
config ATM_NICSTAR
tristate "IDT 77201 (NICStAR) (ForeRunnerLE)"
depends on PCI
......@@ -244,30 +214,6 @@ config ATM_IDT77252_USE_SUNI
depends on ATM_IDT77252
default y
config ATM_HORIZON
tristate "Madge Horizon [Ultra] (Collage PCI 25 and Collage PCI 155 Client)"
depends on PCI && VIRT_TO_BUS
help
This is a driver for the Horizon chipset ATM adapter cards once
produced by Madge Networks Ltd. Say Y (or M to compile as a module
named horizon) here if you have one of these cards.
config ATM_HORIZON_DEBUG
bool "Enable debugging messages"
depends on ATM_HORIZON
help
Somewhat useful debugging messages are available. The choice of
messages is controlled by a bitmap. This may be specified as a
module argument (kernel command line argument as well?), changed
dynamically using an ioctl (not yet) or changed by sending the
string "Dxxxx" to VCI 1023 (where x is a hex digit). See the file
<file:drivers/atm/horizon.h> for the meanings of the bits in the
mask.
When active, these messages can have a significant impact on the
speed of the driver, and the size of your syslog files! When
inactive, they will have only a modest impact on performance.
config ATM_IA
tristate "Interphase ATM PCI x575/x525/x531"
depends on PCI
......
......@@ -5,9 +5,7 @@
fore_200e-y := fore200e.o
obj-$(CONFIG_ATM_ZATM) += zatm.o uPD98402.o
obj-$(CONFIG_ATM_NICSTAR) += nicstar.o
obj-$(CONFIG_ATM_HORIZON) += horizon.o
obj-$(CONFIG_ATM_IA) += iphase.o suni.o
obj-$(CONFIG_ATM_FORE200E) += fore_200e.o
obj-$(CONFIG_ATM_ENI) += eni.o suni.o
......@@ -26,7 +24,6 @@ endif
obj-$(CONFIG_ATM_DUMMY) += adummy.o
obj-$(CONFIG_ATM_TCP) += atmtcp.o
obj-$(CONFIG_ATM_FIRESTREAM) += firestream.o
obj-$(CONFIG_ATM_LANAI) += lanai.o
obj-$(CONFIG_ATM_HE) += he.o
......
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// SPDX-License-Identifier: GPL-2.0-only
/* drivers/atm/uPD98402.c - NEC uPD98402 (PHY) declarations */
/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/atmdev.h>
#include <linux/sonet.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/atomic.h>
#include "uPD98402.h"
#if 0
#define DPRINTK(format,args...) printk(KERN_DEBUG format,##args)
#else
#define DPRINTK(format,args...)
#endif
struct uPD98402_priv {
struct k_sonet_stats sonet_stats;/* link diagnostics */
unsigned char framing; /* SONET/SDH framing */
int loop_mode; /* loopback mode */
spinlock_t lock;
};
#define PRIV(dev) ((struct uPD98402_priv *) dev->phy_data)
#define PUT(val,reg) dev->ops->phy_put(dev,val,uPD98402_##reg)
#define GET(reg) dev->ops->phy_get(dev,uPD98402_##reg)
static int fetch_stats(struct atm_dev *dev,struct sonet_stats __user *arg,int zero)
{
struct sonet_stats tmp;
int error = 0;
atomic_add(GET(HECCT),&PRIV(dev)->sonet_stats.uncorr_hcs);
sonet_copy_stats(&PRIV(dev)->sonet_stats,&tmp);
if (arg) error = copy_to_user(arg,&tmp,sizeof(tmp));
if (zero && !error) {
/* unused fields are reported as -1, but we must not "adjust"
them */
tmp.corr_hcs = tmp.tx_cells = tmp.rx_cells = 0;
sonet_subtract_stats(&PRIV(dev)->sonet_stats,&tmp);
}
return error ? -EFAULT : 0;
}
static int set_framing(struct atm_dev *dev,unsigned char framing)
{
static const unsigned char sonet[] = { 1,2,3,0 };
static const unsigned char sdh[] = { 1,0,0,2 };
const char *set;
unsigned long flags;
switch (framing) {
case SONET_FRAME_SONET:
set = sonet;
break;
case SONET_FRAME_SDH:
set = sdh;
break;
default:
return -EINVAL;
}
spin_lock_irqsave(&PRIV(dev)->lock, flags);
PUT(set[0],C11T);
PUT(set[1],C12T);
PUT(set[2],C13T);
PUT((GET(MDR) & ~uPD98402_MDR_SS_MASK) | (set[3] <<
uPD98402_MDR_SS_SHIFT),MDR);
spin_unlock_irqrestore(&PRIV(dev)->lock, flags);
return 0;
}
static int get_sense(struct atm_dev *dev,u8 __user *arg)
{
unsigned long flags;
unsigned char s[3];
spin_lock_irqsave(&PRIV(dev)->lock, flags);
s[0] = GET(C11R);
s[1] = GET(C12R);
s[2] = GET(C13R);
spin_unlock_irqrestore(&PRIV(dev)->lock, flags);
return (put_user(s[0], arg) || put_user(s[1], arg+1) ||
put_user(s[2], arg+2) || put_user(0xff, arg+3) ||
put_user(0xff, arg+4) || put_user(0xff, arg+5)) ? -EFAULT : 0;
}
static int set_loopback(struct atm_dev *dev,int mode)
{
unsigned char mode_reg;
mode_reg = GET(MDR) & ~(uPD98402_MDR_TPLP | uPD98402_MDR_ALP |
uPD98402_MDR_RPLP);
switch (__ATM_LM_XTLOC(mode)) {
case __ATM_LM_NONE:
break;
case __ATM_LM_PHY:
mode_reg |= uPD98402_MDR_TPLP;
break;
case __ATM_LM_ATM:
mode_reg |= uPD98402_MDR_ALP;
break;
default:
return -EINVAL;
}
switch (__ATM_LM_XTRMT(mode)) {
case __ATM_LM_NONE:
break;
case __ATM_LM_PHY:
mode_reg |= uPD98402_MDR_RPLP;
break;
default:
return -EINVAL;
}
PUT(mode_reg,MDR);
PRIV(dev)->loop_mode = mode;
return 0;
}
static int uPD98402_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
{
switch (cmd) {
case SONET_GETSTATZ:
case SONET_GETSTAT:
return fetch_stats(dev,arg, cmd == SONET_GETSTATZ);
case SONET_SETFRAMING:
return set_framing(dev, (int)(unsigned long)arg);
case SONET_GETFRAMING:
return put_user(PRIV(dev)->framing,(int __user *)arg) ?
-EFAULT : 0;
case SONET_GETFRSENSE:
return get_sense(dev,arg);
case ATM_SETLOOP:
return set_loopback(dev, (int)(unsigned long)arg);
case ATM_GETLOOP:
return put_user(PRIV(dev)->loop_mode,(int __user *)arg) ?
-EFAULT : 0;
case ATM_QUERYLOOP:
return put_user(ATM_LM_LOC_PHY | ATM_LM_LOC_ATM |
ATM_LM_RMT_PHY,(int __user *)arg) ? -EFAULT : 0;
default:
return -ENOIOCTLCMD;
}
}
#define ADD_LIMITED(s,v) \
{ atomic_add(GET(v),&PRIV(dev)->sonet_stats.s); \
if (atomic_read(&PRIV(dev)->sonet_stats.s) < 0) \
atomic_set(&PRIV(dev)->sonet_stats.s,INT_MAX); }
static void stat_event(struct atm_dev *dev)
{
unsigned char events;
events = GET(PCR);
if (events & uPD98402_PFM_PFEB) ADD_LIMITED(path_febe,PFECB);
if (events & uPD98402_PFM_LFEB) ADD_LIMITED(line_febe,LECCT);
if (events & uPD98402_PFM_B3E) ADD_LIMITED(path_bip,B3ECT);
if (events & uPD98402_PFM_B2E) ADD_LIMITED(line_bip,B2ECT);
if (events & uPD98402_PFM_B1E) ADD_LIMITED(section_bip,B1ECT);
}
#undef ADD_LIMITED
static void uPD98402_int(struct atm_dev *dev)
{
static unsigned long silence = 0;
unsigned char reason;
while ((reason = GET(PICR))) {
if (reason & uPD98402_INT_LOS)
printk(KERN_NOTICE "%s(itf %d): signal lost\n",
dev->type,dev->number);
if (reason & uPD98402_INT_PFM) stat_event(dev);
if (reason & uPD98402_INT_PCO) {
(void) GET(PCOCR); /* clear interrupt cause */
atomic_add(GET(HECCT),
&PRIV(dev)->sonet_stats.uncorr_hcs);
}
if ((reason & uPD98402_INT_RFO) &&
(time_after(jiffies, silence) || silence == 0)) {
printk(KERN_WARNING "%s(itf %d): uPD98402 receive "
"FIFO overflow\n",dev->type,dev->number);
silence = (jiffies+HZ/2)|1;
}
}
}
static int uPD98402_start(struct atm_dev *dev)
{
DPRINTK("phy_start\n");
if (!(dev->phy_data = kmalloc(sizeof(struct uPD98402_priv),GFP_KERNEL)))
return -ENOMEM;
spin_lock_init(&PRIV(dev)->lock);
memset(&PRIV(dev)->sonet_stats,0,sizeof(struct k_sonet_stats));
(void) GET(PCR); /* clear performance events */
PUT(uPD98402_PFM_FJ,PCMR); /* ignore frequency adj */
(void) GET(PCOCR); /* clear overflows */
PUT(~uPD98402_PCO_HECC,PCOMR);
(void) GET(PICR); /* clear interrupts */
PUT(~(uPD98402_INT_PFM | uPD98402_INT_ALM | uPD98402_INT_RFO |
uPD98402_INT_LOS),PIMR); /* enable them */
(void) fetch_stats(dev,NULL,1); /* clear kernel counters */
atomic_set(&PRIV(dev)->sonet_stats.corr_hcs,-1);
atomic_set(&PRIV(dev)->sonet_stats.tx_cells,-1);
atomic_set(&PRIV(dev)->sonet_stats.rx_cells,-1);
return 0;
}
static int uPD98402_stop(struct atm_dev *dev)
{
/* let SAR driver worry about stopping interrupts */
kfree(PRIV(dev));
return 0;
}
static const struct atmphy_ops uPD98402_ops = {
.start = uPD98402_start,
.ioctl = uPD98402_ioctl,
.interrupt = uPD98402_int,
.stop = uPD98402_stop,
};
int uPD98402_init(struct atm_dev *dev)
{
DPRINTK("phy_init\n");
dev->phy = &uPD98402_ops;
return 0;
}
MODULE_LICENSE("GPL");
EXPORT_SYMBOL(uPD98402_init);
static __init int uPD98402_module_init(void)
{
return 0;
}
module_init(uPD98402_module_init);
/* module_exit not defined so not unloadable */
/* SPDX-License-Identifier: GPL-2.0 */
/* drivers/atm/uPD98402.h - NEC uPD98402 (PHY) declarations */
/* Written 1995 by Werner Almesberger, EPFL LRC */
#ifndef DRIVERS_ATM_uPD98402_H
#define DRIVERS_ATM_uPD98402_H
/*
* Registers
*/
#define uPD98402_CMR 0x00 /* Command Register */
#define uPD98402_MDR 0x01 /* Mode Register */
#define uPD98402_PICR 0x02 /* PHY Interrupt Cause Register */
#define uPD98402_PIMR 0x03 /* PHY Interrupt Mask Register */
#define uPD98402_ACR 0x04 /* Alarm Cause Register */
#define uPD98402_ACMR 0x05 /* Alarm Cause Mask Register */
#define uPD98402_PCR 0x06 /* Performance Cause Register */
#define uPD98402_PCMR 0x07 /* Performance Cause Mask Register */
#define uPD98402_IACM 0x08 /* Internal Alarm Cause Mask Register */
#define uPD98402_B1ECT 0x09 /* B1 Error Count Register */
#define uPD98402_B2ECT 0x0a /* B2 Error Count Register */
#define uPD98402_B3ECT 0x0b /* B3 Error Count Regster */
#define uPD98402_PFECB 0x0c /* Path FEBE Count Register */
#define uPD98402_LECCT 0x0d /* Line FEBE Count Register */
#define uPD98402_HECCT 0x0e /* HEC Error Count Register */
#define uPD98402_FJCT 0x0f /* Frequence Justification Count Reg */
#define uPD98402_PCOCR 0x10 /* Perf. Counter Overflow Cause Reg */
#define uPD98402_PCOMR 0x11 /* Perf. Counter Overflow Mask Reg */
#define uPD98402_C11T 0x20 /* C11T Data Register */
#define uPD98402_C12T 0x21 /* C12T Data Register */
#define uPD98402_C13T 0x22 /* C13T Data Register */
#define uPD98402_F1T 0x23 /* F1T Data Register */
#define uPD98402_K2T 0x25 /* K2T Data Register */
#define uPD98402_C2T 0x26 /* C2T Data Register */
#define uPD98402_F2T 0x27 /* F2T Data Register */
#define uPD98402_C11R 0x30 /* C11T Data Register */
#define uPD98402_C12R 0x31 /* C12T Data Register */
#define uPD98402_C13R 0x32 /* C13T Data Register */
#define uPD98402_F1R 0x33 /* F1T Data Register */
#define uPD98402_K2R 0x35 /* K2T Data Register */
#define uPD98402_C2R 0x36 /* C2T Data Register */
#define uPD98402_F2R 0x37 /* F2T Data Register */
/* CMR is at 0x00 */
#define uPD98402_CMR_PFRF 0x01 /* Send path FERF */
#define uPD98402_CMR_LFRF 0x02 /* Send line FERF */
#define uPD98402_CMR_PAIS 0x04 /* Send path AIS */
#define uPD98402_CMR_LAIS 0x08 /* Send line AIS */
/* MDR is at 0x01 */
#define uPD98402_MDR_ALP 0x01 /* ATM layer loopback */
#define uPD98402_MDR_TPLP 0x02 /* PMD loopback, to host */
#define uPD98402_MDR_RPLP 0x04 /* PMD loopback, to network */
#define uPD98402_MDR_SS0 0x08 /* SS0 */
#define uPD98402_MDR_SS1 0x10 /* SS1 */
#define uPD98402_MDR_SS_MASK 0x18 /* mask */
#define uPD98402_MDR_SS_SHIFT 3 /* shift */
#define uPD98402_MDR_HEC 0x20 /* disable HEC inbound processing */
#define uPD98402_MDR_FSR 0x40 /* disable frame scrambler */
#define uPD98402_MDR_CSR 0x80 /* disable cell scrambler */
/* PICR is at 0x02, PIMR is at 0x03 */
#define uPD98402_INT_PFM 0x01 /* performance counter has changed */
#define uPD98402_INT_ALM 0x02 /* line fault */
#define uPD98402_INT_RFO 0x04 /* receive FIFO overflow */
#define uPD98402_INT_PCO 0x08 /* performance counter overflow */
#define uPD98402_INT_OTD 0x20 /* OTD has occurred */
#define uPD98402_INT_LOS 0x40 /* Loss Of Signal */
#define uPD98402_INT_LOF 0x80 /* Loss Of Frame */
/* ACR is as 0x04, ACMR is at 0x05 */
#define uPD98402_ALM_PFRF 0x01 /* path FERF */
#define uPD98402_ALM_LFRF 0x02 /* line FERF */
#define uPD98402_ALM_PAIS 0x04 /* path AIS */
#define uPD98402_ALM_LAIS 0x08 /* line AIS */
#define uPD98402_ALM_LOD 0x10 /* loss of delineation */
#define uPD98402_ALM_LOP 0x20 /* loss of pointer */
#define uPD98402_ALM_OOF 0x40 /* out of frame */
/* PCR is at 0x06, PCMR is at 0x07 */
#define uPD98402_PFM_PFEB 0x01 /* path FEBE */
#define uPD98402_PFM_LFEB 0x02 /* line FEBE */
#define uPD98402_PFM_B3E 0x04 /* B3 error */
#define uPD98402_PFM_B2E 0x08 /* B2 error */
#define uPD98402_PFM_B1E 0x10 /* B1 error */
#define uPD98402_PFM_FJ 0x20 /* frequency justification */
/* IACM is at 0x08 */
#define uPD98402_IACM_PFRF 0x01 /* don't generate path FERF */
#define uPD98402_IACM_LFRF 0x02 /* don't generate line FERF */
/* PCOCR is at 0x010, PCOMR is at 0x11 */
#define uPD98402_PCO_B1EC 0x01 /* B1ECT overflow */
#define uPD98402_PCO_B2EC 0x02 /* B2ECT overflow */
#define uPD98402_PCO_B3EC 0x04 /* B3ECT overflow */
#define uPD98402_PCO_PFBC 0x08 /* PFEBC overflow */
#define uPD98402_PCO_LFBC 0x10 /* LFEVC overflow */
#define uPD98402_PCO_HECC 0x20 /* HECCT overflow */
#define uPD98402_PCO_FJC 0x40 /* FJCT overflow */
int uPD98402_init(struct atm_dev *dev);
#endif
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/* SPDX-License-Identifier: GPL-2.0 */
/* drivers/atm/zatm.h - ZeitNet ZN122x device driver declarations */
/* Written 1995-1998 by Werner Almesberger, EPFL LRC/ICA */
#ifndef DRIVER_ATM_ZATM_H
#define DRIVER_ATM_ZATM_H
#include <linux/skbuff.h>
#include <linux/atm.h>
#include <linux/atmdev.h>
#include <linux/sonet.h>
#include <linux/pci.h>
#define DEV_LABEL "zatm"
#define MAX_AAL5_PDU 10240 /* allocate for AAL5 PDUs of this size */
#define MAX_RX_SIZE_LD 14 /* ceil(log2((MAX_AAL5_PDU+47)/48)) */
#define LOW_MARK 12 /* start adding new buffers if less than 12 */
#define HIGH_MARK 30 /* stop adding buffers after reaching 30 */
#define OFF_CNG_THRES 5 /* threshold for offset changes */
#define RX_SIZE 2 /* RX lookup entry size (in bytes) */
#define NR_POOLS 32 /* number of free buffer pointers */
#define POOL_SIZE 8 /* buffer entry size (in bytes) */
#define NR_SHAPERS 16 /* number of shapers */
#define SHAPER_SIZE 4 /* shaper entry size (in bytes) */
#define VC_SIZE 32 /* VC dsc (TX or RX) size (in bytes) */
#define RING_ENTRIES 32 /* ring entries (without back pointer) */
#define RING_WORDS 4 /* ring element size */
#define RING_SIZE (sizeof(unsigned long)*(RING_ENTRIES+1)*RING_WORDS)
#define NR_MBX 4 /* four mailboxes */
#define MBX_RX_0 0 /* mailbox indices */
#define MBX_RX_1 1
#define MBX_TX_0 2
#define MBX_TX_1 3
struct zatm_vcc {
/*-------------------------------- RX part */
int rx_chan; /* RX channel, 0 if none */
int pool; /* free buffer pool */
/*-------------------------------- TX part */
int tx_chan; /* TX channel, 0 if none */
int shaper; /* shaper, <0 if none */
struct sk_buff_head tx_queue; /* list of buffers in transit */
wait_queue_head_t tx_wait; /* for close */
u32 *ring; /* transmit ring */
int ring_curr; /* current write position */
int txing; /* number of transmits in progress */
struct sk_buff_head backlog; /* list of buffers waiting for ring */
};
struct zatm_dev {
/*-------------------------------- TX part */
int tx_bw; /* remaining bandwidth */
u32 free_shapers; /* bit set */
int ubr; /* UBR shaper; -1 if none */
int ubr_ref_cnt; /* number of VCs using UBR shaper */
/*-------------------------------- RX part */
int pool_ref[NR_POOLS]; /* free buffer pool usage counters */
volatile struct sk_buff *last_free[NR_POOLS];
/* last entry in respective pool */
struct sk_buff_head pool[NR_POOLS];/* free buffer pools */
struct zatm_pool_info pool_info[NR_POOLS]; /* pool information */
/*-------------------------------- maps */
struct atm_vcc **tx_map; /* TX VCCs */
struct atm_vcc **rx_map; /* RX VCCs */
int chans; /* map size, must be 2^n */
/*-------------------------------- mailboxes */
unsigned long mbx_start[NR_MBX];/* start addresses */
dma_addr_t mbx_dma[NR_MBX];
u16 mbx_end[NR_MBX]; /* end offset (in bytes) */
/*-------------------------------- other pointers */
u32 pool_base; /* Free buffer pool dsc (word addr) */
/*-------------------------------- ZATM links */
struct atm_dev *more; /* other ZATM devices */
/*-------------------------------- general information */
int mem; /* RAM on board (in bytes) */
int khz; /* timer clock */
int copper; /* PHY type */
unsigned char irq; /* IRQ */
unsigned int base; /* IO base address */
struct pci_dev *pci_dev; /* PCI stuff */
spinlock_t lock;
};
#define ZATM_DEV(d) ((struct zatm_dev *) (d)->dev_data)
#define ZATM_VCC(d) ((struct zatm_vcc *) (d)->dev_data)
struct zatm_skb_prv {
struct atm_skb_data _; /* reserved */
u32 *dsc; /* pointer to skb's descriptor */
};
#define ZATM_PRV_DSC(skb) (((struct zatm_skb_prv *) (skb)->cb)->dsc)
#endif
......@@ -45,40 +45,6 @@ config BPQETHER
useful if some other computer on your local network has a direct
amateur radio connection.
config DMASCC
tristate "High-speed (DMA) SCC driver for AX.25"
depends on ISA && AX25 && BROKEN_ON_SMP && ISA_DMA_API
depends on VIRT_TO_BUS
help
This is a driver for high-speed SCC boards, i.e. those supporting
DMA on one port. You usually use those boards to connect your
computer to an amateur radio modem (such as the WA4DSY 56kbps
modem), in order to send and receive AX.25 packet radio network
traffic.
Currently, this driver supports Ottawa PI/PI2, Paccomm/Gracilis
PackeTwin, and S5SCC/DMA boards. They are detected automatically.
If you have one of these cards, say Y here and read the AX25-HOWTO,
available from <http://www.tldp.org/docs.html#howto>.
This driver can operate multiple boards simultaneously. If you
compile it as a module (by saying M instead of Y), it will be called
dmascc. If you don't pass any parameter to the driver, all
possible I/O addresses are probed. This could irritate other devices
that are currently not in use. You may specify the list of addresses
to be probed by "dmascc.io=addr1,addr2,..." (when compiled into the
kernel image) or "io=addr1,addr2,..." (when loaded as a module). The
network interfaces will be called dmascc0 and dmascc1 for the board
detected first, dmascc2 and dmascc3 for the second one, and so on.
Before you configure each interface with ifconfig, you MUST set
certain parameters, such as channel access timing, clock mode, and
DMA channel. This is accomplished with a small utility program,
dmascc_cfg, available at
<http://www.linux-ax25.org/wiki/Ax25-tools>. Please be sure to
get at least version 1.27 of dmascc_cfg, as older versions will not
work with the current driver.
config SCC
tristate "Z8530 SCC driver"
depends on ISA && AX25 && ISA_DMA_API
......
......@@ -11,7 +11,6 @@
# Christoph Hellwig <hch@infradead.org>
#
obj-$(CONFIG_DMASCC) += dmascc.o
obj-$(CONFIG_SCC) += scc.o
obj-$(CONFIG_MKISS) += mkiss.o
obj-$(CONFIG_6PACK) += 6pack.o
......
This diff is collapsed.
......@@ -23,50 +23,6 @@ menuconfig WAN
if WAN
# There is no way to detect a comtrol sv11 - force it modular for now.
config HOSTESS_SV11
tristate "Comtrol Hostess SV-11 support"
depends on ISA && m && ISA_DMA_API && INET && HDLC && VIRT_TO_BUS
help
Driver for Comtrol Hostess SV-11 network card which
operates on low speed synchronous serial links at up to
256Kbps, supporting PPP and Cisco HDLC.
The driver will be compiled as a module: the
module will be called hostess_sv11.
# The COSA/SRP driver has not been tested as non-modular yet.
config COSA
tristate "COSA/SRP sync serial boards support"
depends on ISA && m && ISA_DMA_API && HDLC && VIRT_TO_BUS
help
Driver for COSA and SRP synchronous serial boards.
These boards allow to connect synchronous serial devices (for example
base-band modems, or any other device with the X.21, V.24, V.35 or
V.36 interface) to your Linux box. The cards can work as the
character device, synchronous PPP network device, or the Cisco HDLC
network device.
You will need user-space utilities COSA or SRP boards for downloading
the firmware to the cards and to set them up. Look at the
<http://www.fi.muni.cz/~kas/cosa/> for more information. You can also
read the comment at the top of the <file:drivers/net/wan/cosa.c> for
details about the cards and the driver itself.
The driver will be compiled as a module: the
module will be called cosa.
# There is no way to detect a Sealevel board. Force it modular
config SEALEVEL_4021
tristate "Sealevel Systems 4021 support"
depends on ISA && m && ISA_DMA_API && INET && HDLC && VIRT_TO_BUS
help
This is a driver for the Sealevel Systems ACB 56 serial I/O adapter.
The driver will be compiled as a module: the
module will be called sealevel.
# Generic HDLC
config HDLC
tristate "Generic HDLC layer"
......
......@@ -14,9 +14,6 @@ obj-$(CONFIG_HDLC_FR) += hdlc_fr.o
obj-$(CONFIG_HDLC_PPP) += hdlc_ppp.o
obj-$(CONFIG_HDLC_X25) += hdlc_x25.o
obj-$(CONFIG_HOSTESS_SV11) += z85230.o hostess_sv11.o
obj-$(CONFIG_SEALEVEL_4021) += z85230.o sealevel.o
obj-$(CONFIG_COSA) += cosa.o
obj-$(CONFIG_FARSYNC) += farsync.o
obj-$(CONFIG_LAPBETHER) += lapbether.o
......
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* $Id: cosa.h,v 1.6 1999/01/06 14:02:44 kas Exp $ */
/*
* Copyright (C) 1995-1997 Jan "Yenya" Kasprzak <kas@fi.muni.cz>
*/
#ifndef COSA_H__
#define COSA_H__
#include <linux/ioctl.h>
#ifdef __KERNEL__
/* status register - output bits */
#define SR_RX_DMA_ENA 0x04 /* receiver DMA enable bit */
#define SR_TX_DMA_ENA 0x08 /* transmitter DMA enable bit */
#define SR_RST 0x10 /* SRP reset */
#define SR_USR_INT_ENA 0x20 /* user interrupt enable bit */
#define SR_TX_INT_ENA 0x40 /* transmitter interrupt enable bit */
#define SR_RX_INT_ENA 0x80 /* receiver interrupt enable bit */
/* status register - input bits */
#define SR_USR_RQ 0x20 /* user interrupt request pending */
#define SR_TX_RDY 0x40 /* transmitter empty (ready) */
#define SR_RX_RDY 0x80 /* receiver data ready */
#define SR_UP_REQUEST 0x02 /* request from SRP to transfer data
up to PC */
#define SR_DOWN_REQUEST 0x01 /* SRP is able to transfer data down
from PC to SRP */
#define SR_END_OF_TRANSFER 0x03 /* SRP signalize end of
transfer (up or down) */
#define SR_CMD_FROM_SRP_MASK 0x03 /* mask to get SRP command */
/* bits in driver status byte definitions : */
#define SR_RDY_RCV 0x01 /* ready to receive packet */
#define SR_RDY_SND 0x02 /* ready to send packet */
#define SR_CMD_PND 0x04 /* command pending */ /* not currently used */
/* ???? */
#define SR_PKT_UP 0x01 /* transfer of packet up in progress */
#define SR_PKT_DOWN 0x02 /* transfer of packet down in progress */
#endif /* __KERNEL__ */
#define SR_LOAD_ADDR 0x4400 /* SRP microcode load address */
#define SR_START_ADDR 0x4400 /* SRP microcode start address */
#define COSA_LOAD_ADDR 0x400 /* SRP microcode load address */
#define COSA_MAX_FIRMWARE_SIZE 0x10000
/* ioctls */
struct cosa_download {
int addr, len;
char __user *code;
};
/* Reset the device */
#define COSAIORSET _IO('C',0xf0)
/* Start microcode at given address */
#define COSAIOSTRT _IOW('C',0xf1, int)
/* Read the block from the device memory */
#define COSAIORMEM _IOWR('C',0xf2, struct cosa_download *)
/* actually the struct cosa_download itself; this is to keep
* the ioctl number same as in 2.4 in order to keep the user-space
* utils compatible. */
/* Write the block to the device memory (i.e. download the microcode) */
#define COSAIODOWNLD _IOW('C',0xf2, struct cosa_download *)
/* actually the struct cosa_download itself; this is to keep
* the ioctl number same as in 2.4 in order to keep the user-space
* utils compatible. */
/* Read the device type (one of "srp", "cosa", and "cosa8" for now) */
#define COSAIORTYPE _IOR('C',0xf3, char *)
/* Read the device identification string */
#define COSAIORIDSTR _IOR('C',0xf4, char *)
/* Maximum length of the identification string. */
#define COSA_MAX_ID_STRING 128
/* Increment/decrement the module usage count :-) */
/* #define COSAIOMINC _IO('C',0xf5) */
/* #define COSAIOMDEC _IO('C',0xf6) */
/* Get the total number of cards installed */
#define COSAIONRCARDS _IO('C',0xf7)
/* Get the number of channels on this card */
#define COSAIONRCHANS _IO('C',0xf8)
/* Set the driver for the bus-master operations */
#define COSAIOBMSET _IOW('C', 0xf9, unsigned short)
#define COSA_BM_OFF 0 /* Bus-mastering off - use ISA DMA (default) */
#define COSA_BM_ON 1 /* Bus-mastering on - faster but untested */
/* Gets the busmaster status */
#define COSAIOBMGET _IO('C', 0xfa)
#endif /* !COSA_H__ */
// SPDX-License-Identifier: GPL-2.0-only
/* Comtrol SV11 card driver
*
* This is a slightly odd Z85230 synchronous driver. All you need to
* know basically is
*
* Its a genuine Z85230
*
* It supports DMA using two DMA channels in SYNC mode. The driver doesn't
* use these facilities
*
* The control port is at io+1, the data at io+3 and turning off the DMA
* is done by writing 0 to io+4
*
* The hardware does the bus handling to avoid the need for delays between
* touching control registers.
*
* Port B isn't wired (why - beats me)
*
* Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/net.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/if_arp.h>
#include <linux/delay.h>
#include <linux/hdlc.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <net/arp.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/dma.h>
#include <asm/byteorder.h>
#include "z85230.h"
static int dma;
/* Network driver support routines
*/
static inline struct z8530_dev *dev_to_sv(struct net_device *dev)
{
return (struct z8530_dev *)dev_to_hdlc(dev)->priv;
}
/* Frame receive. Simple for our card as we do HDLC and there
* is no funny garbage involved
*/
static void hostess_input(struct z8530_channel *c, struct sk_buff *skb)
{
/* Drop the CRC - it's not a good idea to try and negotiate it ;) */
skb_trim(skb, skb->len - 2);
skb->protocol = hdlc_type_trans(skb, c->netdevice);
skb_reset_mac_header(skb);
skb->dev = c->netdevice;
/* Send it to the PPP layer. We don't have time to process
* it right now.
*/
netif_rx(skb);
}
/* We've been placed in the UP state
*/
static int hostess_open(struct net_device *d)
{
struct z8530_dev *sv11 = dev_to_sv(d);
int err = -1;
/* Link layer up
*/
switch (dma) {
case 0:
err = z8530_sync_open(d, &sv11->chanA);
break;
case 1:
err = z8530_sync_dma_open(d, &sv11->chanA);
break;
case 2:
err = z8530_sync_txdma_open(d, &sv11->chanA);
break;
}
if (err)
return err;
err = hdlc_open(d);
if (err) {
switch (dma) {
case 0:
z8530_sync_close(d, &sv11->chanA);
break;
case 1:
z8530_sync_dma_close(d, &sv11->chanA);
break;
case 2:
z8530_sync_txdma_close(d, &sv11->chanA);
break;
}
return err;
}
sv11->chanA.rx_function = hostess_input;
/*
* Go go go
*/
netif_start_queue(d);
return 0;
}
static int hostess_close(struct net_device *d)
{
struct z8530_dev *sv11 = dev_to_sv(d);
/* Discard new frames
*/
sv11->chanA.rx_function = z8530_null_rx;
hdlc_close(d);
netif_stop_queue(d);
switch (dma) {
case 0:
z8530_sync_close(d, &sv11->chanA);
break;
case 1:
z8530_sync_dma_close(d, &sv11->chanA);
break;
case 2:
z8530_sync_txdma_close(d, &sv11->chanA);
break;
}
return 0;
}
/* Passed network frames, fire them downwind.
*/
static netdev_tx_t hostess_queue_xmit(struct sk_buff *skb,
struct net_device *d)
{
return z8530_queue_xmit(&dev_to_sv(d)->chanA, skb);
}
static int hostess_attach(struct net_device *dev, unsigned short encoding,
unsigned short parity)
{
if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT)
return 0;
return -EINVAL;
}
/* Description block for a Comtrol Hostess SV11 card
*/
static const struct net_device_ops hostess_ops = {
.ndo_open = hostess_open,
.ndo_stop = hostess_close,
.ndo_start_xmit = hdlc_start_xmit,
.ndo_siocwandev = hdlc_ioctl,
};
static struct z8530_dev *sv11_init(int iobase, int irq)
{
struct z8530_dev *sv;
struct net_device *netdev;
/* Get the needed I/O space
*/
if (!request_region(iobase, 8, "Comtrol SV11")) {
pr_warn("I/O 0x%X already in use\n", iobase);
return NULL;
}
sv = kzalloc(sizeof(struct z8530_dev), GFP_KERNEL);
if (!sv)
goto err_kzalloc;
/* Stuff in the I/O addressing
*/
sv->active = 0;
sv->chanA.ctrlio = iobase + 1;
sv->chanA.dataio = iobase + 3;
sv->chanB.ctrlio = -1;
sv->chanB.dataio = -1;
sv->chanA.irqs = &z8530_nop;
sv->chanB.irqs = &z8530_nop;
outb(0, iobase + 4); /* DMA off */
/* We want a fast IRQ for this device. Actually we'd like an even faster
* IRQ ;) - This is one driver RtLinux is made for
*/
if (request_irq(irq, z8530_interrupt, 0,
"Hostess SV11", sv) < 0) {
pr_warn("IRQ %d already in use\n", irq);
goto err_irq;
}
sv->irq = irq;
sv->chanA.private = sv;
sv->chanA.dev = sv;
sv->chanB.dev = sv;
if (dma) {
/* You can have DMA off or 1 and 3 thats the lot
* on the Comtrol.
*/
sv->chanA.txdma = 3;
sv->chanA.rxdma = 1;
outb(0x03 | 0x08, iobase + 4); /* DMA on */
if (request_dma(sv->chanA.txdma, "Hostess SV/11 (TX)"))
goto err_txdma;
if (dma == 1)
if (request_dma(sv->chanA.rxdma, "Hostess SV/11 (RX)"))
goto err_rxdma;
}
/* Kill our private IRQ line the hostess can end up chattering
* until the configuration is set
*/
disable_irq(irq);
/* Begin normal initialise
*/
if (z8530_init(sv)) {
pr_err("Z8530 series device not found\n");
enable_irq(irq);
goto free_dma;
}
z8530_channel_load(&sv->chanB, z8530_dead_port);
if (sv->type == Z85C30)
z8530_channel_load(&sv->chanA, z8530_hdlc_kilostream);
else
z8530_channel_load(&sv->chanA, z8530_hdlc_kilostream_85230);
enable_irq(irq);
/* Now we can take the IRQ
*/
sv->chanA.netdevice = netdev = alloc_hdlcdev(sv);
if (!netdev)
goto free_dma;
dev_to_hdlc(netdev)->attach = hostess_attach;
dev_to_hdlc(netdev)->xmit = hostess_queue_xmit;
netdev->netdev_ops = &hostess_ops;
netdev->base_addr = iobase;
netdev->irq = irq;
if (register_hdlc_device(netdev)) {
pr_err("unable to register HDLC device\n");
free_netdev(netdev);
goto free_dma;
}
z8530_describe(sv, "I/O", iobase);
sv->active = 1;
return sv;
free_dma:
if (dma == 1)
free_dma(sv->chanA.rxdma);
err_rxdma:
if (dma)
free_dma(sv->chanA.txdma);
err_txdma:
free_irq(irq, sv);
err_irq:
kfree(sv);
err_kzalloc:
release_region(iobase, 8);
return NULL;
}
static void sv11_shutdown(struct z8530_dev *dev)
{
unregister_hdlc_device(dev->chanA.netdevice);
z8530_shutdown(dev);
free_irq(dev->irq, dev);
if (dma) {
if (dma == 1)
free_dma(dev->chanA.rxdma);
free_dma(dev->chanA.txdma);
}
release_region(dev->chanA.ctrlio - 1, 8);
free_netdev(dev->chanA.netdevice);
kfree(dev);
}
static int io = 0x200;
static int irq = 9;
module_param_hw(io, int, ioport, 0);
MODULE_PARM_DESC(io, "The I/O base of the Comtrol Hostess SV11 card");
module_param_hw(dma, int, dma, 0);
MODULE_PARM_DESC(dma, "Set this to 1 to use DMA1/DMA3 for TX/RX");
module_param_hw(irq, int, irq, 0);
MODULE_PARM_DESC(irq, "The interrupt line setting for the Comtrol Hostess SV11 card");
MODULE_AUTHOR("Alan Cox");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Modular driver for the Comtrol Hostess SV11");
static struct z8530_dev *sv11_unit;
static int sv11_module_init(void)
{
sv11_unit = sv11_init(io, irq);
if (!sv11_unit)
return -ENODEV;
return 0;
}
module_init(sv11_module_init);
static void sv11_module_cleanup(void)
{
if (sv11_unit)
sv11_shutdown(sv11_unit);
}
module_exit(sv11_module_cleanup);
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/* atm_zatm.h - Driver-specific declarations of the ZATM driver (for use by
driver-specific utilities) */
/* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */
#ifndef LINUX_ATM_ZATM_H
#define LINUX_ATM_ZATM_H
/*
* Note: non-kernel programs including this file must also include
* sys/types.h for struct timeval
*/
#include <linux/atmapi.h>
#include <linux/atmioc.h>
#define ZATM_GETPOOL _IOW('a',ATMIOC_SARPRV+1,struct atmif_sioc)
/* get pool statistics */
#define ZATM_GETPOOLZ _IOW('a',ATMIOC_SARPRV+2,struct atmif_sioc)
/* get statistics and zero */
#define ZATM_SETPOOL _IOW('a',ATMIOC_SARPRV+3,struct atmif_sioc)
/* set pool parameters */
struct zatm_pool_info {
int ref_count; /* free buffer pool usage counters */
int low_water,high_water; /* refill parameters */
int rqa_count,rqu_count; /* queue condition counters */
int offset,next_off; /* alignment optimizations: offset */
int next_cnt,next_thres; /* repetition counter and threshold */
};
struct zatm_pool_req {
int pool_num; /* pool number */
struct zatm_pool_info info; /* actual information */
};
#define ZATM_OAM_POOL 0 /* free buffer pool for OAM cells */
#define ZATM_AAL0_POOL 1 /* free buffer pool for AAL0 cells */
#define ZATM_AAL5_POOL_BASE 2 /* first AAL5 free buffer pool */
#define ZATM_LAST_POOL ZATM_AAL5_POOL_BASE+10 /* max. 64 kB */
#define ZATM_TIMER_HISTORY_SIZE 16 /* number of timer adjustments to
record; must be 2^n */
#endif
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