Commit 0487bbb4 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/pm: add documentation for pp_od_clock_voltage for APUs

APUs only support adjusting the SCLK domain.
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cfd053be
......@@ -735,6 +735,14 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
* - a list of valid ranges for sclk, mclk, and voltage curve points
* labeled OD_RANGE
*
* < For APUs >
*
* Reading the file will display:
*
* - minimum and maximum engine clock labeled OD_SCLK
*
* - a list of valid ranges for sclk labeled OD_RANGE
*
* To manually adjust these settings:
*
* - First select manual using power_dpm_force_performance_level
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment